The synchrotron x ray lithography (XRL) project described was conducted as a learning and feasibility vehicle for gate level lithography in support of IBM's most advanced CMOS logic programs. An electrically probable multilevel lithography test site was developed and characterized to exercise critical design, mask manufacture, alignment, exposure, and metrology issues in the 150 - 350 nm linewidth range. A fully capped silicided polysilicon gate stack was chosen for the electrical measurements in order to develop and demonstrate the XRL and related reactive ion etch process on a realistic, product-like substrate. This paper addresses test site design issues, elaborates on the mask manufacturing process, and presents SEM and electrical data from wafers processed at IBM's Advanced Semiconductor Technology Center. The data presented demonstrate the feasibility of supporting early device development and process integration with XRL and highlight the need for high resolution, defect free, proximity corrected masks to fully exploit the capabilities of x ray lithography.