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16 May 1994 Lithographic strategies for 0.35-μm poly gates for random logic applications
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Abstract
DUV lithography using wet developable resists can be used for the poly gate definition of 0.35micrometers CMOS processes. Four years ago, we demonstrated a resolution of 0.3micrometers L/S obtained with Shipley XP 89131 resist. Nevertheless, in order to make this and other resist processes suitable for real device applications, several problems had to be overcome. First, reflective notching and linewidth variations over steps turned out to be an important limitation. Some strategy to reduce this sensitivity to reflections has to be applied. Furthermore, in order to obtain a stable and reproducible lithographic process, process latitudes should be wide. Furthermore, a comparison between positive tone and negative tone resists is made with respect to their suitability for poly gate patterning. It was observed that negatively sloped resist profiles, as a result of the use of negative tone resists, create a controllability problem during in-line SEM inspections, and such profiles result in positively sloped poly profiles after etching. Positive tone resists have positively sloped resist profiles, but they require the use of a bright field mask, and hence reflections are much more of a problem. Also, positive tone resist are more sensitive to the delay effects.
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Maaike Op de Beeck, Veerle Van Driessche, Luc Van den Hove, and Han J. Dijkstra "Lithographic strategies for 0.35-μm poly gates for random logic applications", Proc. SPIE 2195, Advances in Resist Technology and Processing XI, (16 May 1994); https://doi.org/10.1117/12.175356
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