Advances in memory IC technology for dynamic random access memory (DRAM) devices have been achieved by increasing the number of memory cells occupying a certain chip area, consequently increasing memory size. Current methods of implementation include vertical topography, which relies on reducing the cell's thickness while increasing its depth in order to maintain the same capacitance of stored electrical charges. As the memory size on DRAM devices rises, memory cells have to reach deeper levels, thus making the process of measuring depth even harder. A novel metrology technique, which utilizes both 2-D diffraction analysis and multivariate statistical methods to measure deep trench depth, is discussed in this work. This technique was applied to two DRAM product wafers, and successful prediction of trench depth was obtained for both wafers with an accuracy of +/- 0.04 micrometers , or +/- 0.56% variation.
We investigated the effect of dissimilar materials on submicron linewidth measurements that are made from phase images. When the relative reflectivity is low, errors are introduced into linewidth measurements made directly from phase images. Two calibration algorithms were developed based on the theoretical modeling of a partially coherent optical system. There was good agreement between the experimental results and the theoretical predictions.
Progress is being made on the development of a deep UV interferometric microscope to operate at a wavelength of 248 nm. The eventual aim is to make measurements of 0.18 - 0.25 micrometers gate structures. The microscope employs a mercury vapor light source, an image intensifier with a CCD or vidicon camera, and quartz lenses. The device is based on the Mirau correlation microscope, and uses a Mirau interferometer with a new type of radially sectored beamsplitter. Feasibility has been demonstrated.
Images of a microlithographic sample obtained using a new near field scanning optical microscope (NSOM) that uses force regulation of the sample-tip separation are presented. The NSOM is a research instrument fitted with a metal covered glass tip probe that defines a small aperture at the sharp end. The aperture is estimated to be on the order of 100 nanometers in diameter resulting in a resolution exceeding that of diffraction limited systems. This form of microscopy can be done both in the transmission and the reflection modes. The force regulation mechanism produces a simultaneously obtained scanned force microscope image of the topography thus permitting correlative imaging of the sample. The samples are imaged in transmission and reflection near field optical format, with white light and with coherent light. The results are compared with other forms of IC imaging and characterization, namely scanned force microscopy and scanning electron microscopy.
A novel submicron dimension reference for calibrating electron-beam metrology systems has been developed. A fine rectangular-profile diffraction grating fabricated by laser interferometer lithography and anisotropic chemical etching of (110) crystalline silicon satisfies any conditions for submicron dimension reference. In this reference, pitch size of about 0.2 micrometers is easily obtained by laser interferometer lithography with an accuracy, shown by optical diffraction measurement, of within 1 nm. This reference also satisfies several requirements for electron-beam metrology systems. It is stable and free from build-up of charge under electron-beam irradiation because it is fabricated from a conductive silicon single crystal. Also it generates high-contrast secondary electron signals due to high-aspect ratio grating profile. Evaluation of this reference by optical diffraction measurement and electron- beam CD measurements show high performance for submicron dimension calibration. In electron-beam CD measurements, the deviation of repeated measurements is under 5 nm within 3 (sigma) .
A scanning electron microscope (SEM) can be used to measure the dimensions of the microlithographic features of integrated circuits. However, without a good model of the electron-beam/specimen interaction, accurate edge location cannot be obtained. A Monte Carlo code has been developed to model the interaction of an electron beam with a line lithographically produced on a multi-layer substrate. The purpose of the code is to enable one to extract the edge position of a line from SEM measurements. It is based on prior codes developed at NIST, but with a new formulation for the atomic scattering cross sections and the inclusion of a method to simulate edge roughness or rounding. The code is currently able to model the transmitted and backscattered electrons, and the results from the code have been applied to the analysis of electron transmission through a gold line on a thin silicon substrate, such as used in an x-ray lithographic mask.
To evaluate the rigorousness of existing algorithms for critical dimension (CD) linewidth measurements in the SEM, a Monte Carlo program was developed to model the topographic signal of line-and-space patterns for both backscattered and secondary electrons. The line cross-section is assumed to be a perfect trapezoid. In this paper we present the results of the modeling of submicron photoresist lines on a silicon substrate for primary beam energies <EQ 1 keV and for various slope angles, pitches, and beam sizes. The simulated profiles are used to quantify the systematic errors introduced by commonly used linewidth measuring algorithms. The simulated secondary electron profiles are compared with reality by recording top-view and cross-section SEM images of submicron resist lines on Si. For comparison reasons only, we also recorded the same images after gold-coating the specimen, thus eliminating charging effects. The experimental profiles are very similar to the simulated profiles, but the geometrical imperfectness of the resist lines inhibits a quantitative comparison.
Wafer inspection systems using a scanning electron beam are utilized for the observation of patterns in microcircuits. The spatial resolution that is required for these systems has been decreasing every three years by a factor of 0.7 corresponding to the scaling of the critical feature sizes. A resolving power above 5 nm is necessary for quarter micron devices such as the 256 Mbit DRAM. Shortening the working distance (WD) is an effective way to improve the resolving power. However, conventional systems limit the WD since the specimen stage is separated from the magnetic circuits of the objective lens. In order to satisfy the requirements for the resolution, we have tested for a new E-beam wafer inspection system `in-lens SEM.' The `in-lens SEM' has a large objective lens that serves as a specimen chamber, and the specimen stage is built in the objective lens. As a result, the WD of `ultimate 0' can be realized. This is one of the most remarkable features of this system.
Critical dimension measurements for state of the art sub-micron semiconductor processes are typically accomplished using automated scanning electron microscopes. The measurements generated in these instruments are primarily based upon secondary electron imaging techniques. Several issues associated with this mode of SEM imaging that directly impact the precision and accuracy of the measurement system are reviewed. These issues have led to the current investigation of SEM metrology utilizing backscattered electron imaging techniques. The implications and differences between SE and BSE imaging techniques and their relation to CD measurements are discussed in this work.
The characteristics of BSE emission at low beam energies (0.5 to 5 kV) are discussed with reference to signal intensity, topographic contrast, material contrast, charging phenomena, and metrology issues. Experimental results are presented for a back-scattered electron (BSE) detector that has been developed for viewing deep trenches and high-aspect contact holes in the CD-SEM metrology applications.
Low-loss electron (LLE) imaging has been shown to have significant advantages over both secondary electron and conventional backscattered electron imaging for the purposes of inspection and critical dimension metrology of integrated circuits. LLE images had high- resolution, good atomic contrast and fewer charging artifacts. Further, they were easily optimized using Monte Carlo simulations; and the optimized LLE images showed excellent precision, accuracy, and linearity in both process control and focus-exposure applications.
Metrology of critical dimensions in an automated fashion requires that stage precision is such that interwafer repeatability be better than approximately 1 micrometers . This limits the need for pattern recognition. Review applications require that the stage can `blind'-navigate to a specific location as a result of an electrical test or defect detection. The extensive use of modal analysis in both the pre-design and test phases has shown the value of this technique, the measured and the pre-calculated resonant (eigen) frequencies being within 5% of each other. We implemented a fully automated mapping procedure that uses pattern recognition techniques to map the encoder errors and global errors relative to a reference wafer. A correction program has been built to provide absolute accuracy results typically of 1.5 micrometers 3 (sigma) with an offset less than 0.2 micrometers over 25 mm (die size) and 2 micrometers 3 (sigma) with a 0.5 micrometers offset for the whole wafer.
Mask defect specification is derived from the needs of IC makers. It is primarily based on the wafer design rule. The specification relates to many issues that are usually defined and tested separately. In this paper we are concerned with the relation between edge defect specification and CD tolerance. The main problem with a combination of errors is how to handle the case of two errors of different kinds that are both below the specification, when considered separately, but their total change in edge position is larger than the edge defect specification. By convention, CD errors are automatically eliminated during automatic defect inspection by bias correction. Therefore, the inspection machine actually processes a database representation that matches the scanned image of the inspected die as best as possible. Thus the detection of combinations of global CD errors and edge extensions is prevented. An analysis of the problem is presented. A novel approach is suggested by which the user may optionally take into account CD errors together with edge defects during inspection. The experimental results are reported and initial conclusions are drawn.
Many kinds of systems are available to detect defects on patterned wafers using very different technical methods. The fastest and most widespread of these use the laser scattering technique. Some suppliers have now introduced many improvements into this laser scattering tool technique. The latest of these improvements involves multi-thresholding and Fourier masking. We evaluate the quality and limitation of these techniques. The results are obtained on the one hand under real conditions on the 0.8 and 0.5 micron products. On the other hand we have developed a special design on a reticule to ensure good reproducibility and to help us understand the running of the equipment. Sensitivity has been extensively studied. This criterion is very dependent on many parameters. The tool is sensitive to the orientation of the wafer. The capture rate on the design of known simulated defects gives results when using repetitive designs. The optical signal is difficult to correlate with the dimensional parameter of the defect. This feature depends on the technology of the system. This point is crucial when moving from the role of monitoring tool to one of defect tool.
Focused ion beam repair of opaque defects in 5X reticles produces post repair stains which result in ghost defects in wafer prints produced at G-line, I-line, and DUV wavelengths. These stains can be removed using a post repair plasma process which restores transmission to almost 100%. However, a new in situ process is preferred which reduces stains to acceptable levels. The key to the new process is an understanding of factors affecting sputter yield. The effectiveness of the in situ antistain procedure is demonstrated through wafer lithography at all three wavelengths showing an absence of ghost defects following repair.
As the density of VLSI circuits increases, the proximity effect has been one of the critical issues in optical lithography. In general, the linewidth difference between dense and isolated patterns corresponds to 0.08 micrometers when a conventional i-line single resist process using a 0.54 NA is applied to the half-micron geometry on a flat wafer. Therefore, this linewidth difference has significantly affected the process stability in the real process applications. This paper describes the dependency of the proximity effects on the pattern size, line and space duty ratio, kinds of substrate film, defocus effect during exposure, and resist process conditions related to the variation of the resist thickness and develop time. Critical dimension (CD) deviation caused by the different latent image contrast is also experimentally monitored using two different photoresists. A simulation is performed for the purpose of obtaining the optimum resist thickness to reduce CD difference caused by the variations of resist thickness in the real topography.
We have developed an expert system based on statistical knowledge and photolithographic knowledge. The philosophy of our system is to minimize the number and the cost of the experiments to reach a final objective or to show that the process will never achieve it. The system suggests intermediate objectives to test stability of the resist sensitivity before testing the final objective i.e., an optimized process point for the photolithography of a specific level. When a partial objective is completed the system proposes a goal involving more expensive experiments, and so on, until the final objective is reached. In this paper we demonstrate the capability of our system on the more advanced photolithographic processes. The first example is the study of delay time effect on positive deep UV resists. The second example is the optimization of a deep UV negative process for the gate level. As a conclusion, a comparison between the necessary steps required for this study and a standard approach is done.
Gallium arsenide metal semiconductor field effect transistors (GaAs MESFETs) are used in analog microwave monolithic integrated circuits (MMICs) because of their high frequency response. Common applications for MMICs include low noise and power amplifiers for use in satellite communication and missile guidance systems. The performance of MESFETs is improved with smaller gate lengths, but to consistently achieve the highest performance, control methods must be in place for the critical processes. Gate length control is the key parameter in maintaining the rf performance and a lack of gate pinch off is the major yield loss category. This paper describes the process and the tools that Texas Instruments uses to monitor the critical parameters. It also describes the control methods and reviews the major contributors to variations in the process.
In this work critical dimension (CD) and site focal plane deviation (SFPD) measurements were made on a patterned resist test structure with 0.8 micron dense lines with a pitch of 1.6 micrometers . The CD and SFPD were tracked through all critical wafer processing steps. The range in SFPD was negligible throughout front end processing, with average SFPDs less than 0.25 microns. Significant increase in the mean and variance of SFPD was observed at later process modules. An increase in the SFPD directly reduces the focus budget, resulting in an increase in the variation of the CD across a field as well as a degradation of the resist profile. Within-field CD variation (3 sigma) for a SFPD of 0.05 micrometers was observed to be less than 0.03 micrometers (30 measurement sites within a field) whereas the three sigma CD variation for a SFPD of 3.8 micrometers was observed to be 0.45 micrometers . Two-dimensional and 3-D graphical correlations are presented, and the use of the SFPD/CD correlation technique to photolithographic process optimization is discussed.
A phase-lock-in technique is used for direct monitoring of electron beam intensity profile in 2- D in the scanning electron microscope based electron beam lithography system. Faraday cup assembly, modulated ramp generator, and data-acquisition software necessary for beam parameter measurements were developed. The electron beam diameter of 100 angstrom dimension at 50 pA current with the accuracy +/- 24 angstrom was measured. The effect of variation of operating conditions of SEM on the diameter and shape was observed and studied. The set-up developed enables the user to take in-situ measurement and control e-beam parameters.
This paper describes a new method for monitoring the performance of metrology systems. The objective of the technique is to both identify deviant performance and estimate the likely cause. The method is driven by the assumption that all variation in a measurement system is systematic until proven random. This assumption in turn guides the choice of sampling plan and analysis to extract the maximum amount of information possible from a given number of measurements. Diagnostic capability is achieved by selecting a sampling plan which yields data for estimates of all known error modes of the instrument. Consequently, somewhat larger sampling plans are required and the technique is generally more appropriate for automated measurement systems. The concept is illustrated by example using automated scanning electron microscopes used for critical dimension measurement in the semiconductor manufacturing process. Experimental results illustrating the response of the monitor to programmed deviation are presented.
In the development and manufacture of integrated circuits, as requirements push closer to the theoretical (Rayleigh) limit of performance, depth of focus decreases as resolution is increased. The advent of easily accessible tools for image processing suggest that a quantitative determination of best focus is possible. Workers in this laboratory have developed a technique for determining `best focus' using 2-D Fourier power spectra of SEM images of exposed patterns. From this a `figure of merit' is extracted by assuming that what is desired is to maximize orthogonal edges (from `as-drawn' features) and minimize intermediate features (edge rounding). This has been shown to provide a quantitative value that is consistent with an `expert' assessment of the same images. The system is consistent with automation of the process, eliminating the need to record hard-copy images for `expert' evaluation.
The evaluation of processes for 0.35 micron poly gate patterning using DUV negative resist is described. The advantages and drawbacks of negative versus positive resist, for linewidth control, are outlined. The necessity of using top or bottom anti-reflective coatings is examined. The performance of the different process schemes is compared, with regard to linewidth control over isolation topography, reflective notching control, line edge roughness, and line length control. Although the negative tone resist showed good process latitude and performed well, with regard to notching behavior, the high transmission of the resist led to unacceptable linewidth variations unless a bottom anti-reflective coating was used.
The Orbot wafer inspection system is designed to implement an automatic defect detection strategy. It employs the unique Perspective Darkfield Imaging (PDITM) technology to produce simultaneously four different high resolution images of the scanned wafer area. In PDI images defects appear in multiple perspectives as isolated, bright `stars' on a mostly dark background. This allows high detection sensitivity of 0.1 micrometers defects on advanced complex, dense wafers (0.35 micrometers design rule) with topography. In this paper we demonstrate the advantages of PDI as implemented in the Orbot WF-710. The tool used to emphasize and exploit the very high signal to noise ratio for small defects is the PDI histogram. It is shown that on these histograms submicron defects as small as 0.15 micrometers are significantly separated from the normal wafer pixel population and so can be easily detected. Furthermore PDI histograms can be considered as being the `finger print' of a particular product and layer. The natural extension of this is that PDI histograms can be used to monitor process anomalies not reflected by defects, and so trace process instabilities. A brief description of PDI technology is provided. PDI histograms and the experimental results are set out.
As the design rule of devices continues to shrink, the overlay margin of layer to layer continues to become smaller. Inter-field error of overlay can be compensated by alignment parameters of the exposure system, but intra-field error of overlay is very difficult to change within a field. This paper discusses the intra-field overlay error, especially that caused by oxidation and deposition processes of a metal-oxide-silicon (MOS) integrated circuit device. In an experiment, to analyze process induced affects on the intra-field overlay error of device, we monitored thermal process, film deposition, oxidation, lithography, etching, and implantation process and pursued the trend and sources of intra-field overlay error generated in wafer process. We analyzed the affects of film stress and thermal process by measuring box and box overlay marks using the KLA metrology system at the etch process step.
Moire alignment and overlay measurement techniques with nm-scale precision are demonstrated. Using 0.47-micrometers pitch gratings, a 1-nm alignment resolution is demonstrated. A novel double-period moire grating is used to provide both coarse (approximately 10 micrometers ) and fine (approximately 1 micrometers ) capture ranges for integration with existing stage positioning systems. A new diffraction-order interferometry technique for nm-precision remote overlay readout, with potential application to latent image structures immediately after exposure, is demonstrated.
Overlay budgets for advanced products are in the range of 100 to 150 nm; mean plus 3 sigma. It is crucial that the metrology tool contribute a minimal amount of error since the majority of the overlay specification is used up by the stepper errors. Most of the newer tools available today have no problem in achieving this criterion, even at these tight specifications. However, certain semiconductor processes produce overlay targets that are very difficult to measure such as grainy metal, tungsten plugged vias, and well planarized substrates. These substrates can be, roughly, grouped into two categories of `low contrast' and `distorted targets.' In the case of the low contrast targets, the signal to noise ratio is very low and the metrology tool has difficulty in identifying the actual target. Distorted targets can be measured but appear different to the metrology tool from one location to the other due to random distortions of the target edges thus producing erroneous measurements.
Using a commercially available software package, overlay sample plans were evaluated for use in a 0.5 micrometers manufacturing process. Monitor wafers were patterned using a two layer overlay evaluation reticle set. Known values of both grid and field errors were entered into the stepper during the exposure of the second layer to force a controlled range of misregistration. Extensive overlay measurements were collected from these wafers. These detailed data sets were modeled to define the relationships between distortion coefficients reported by the software and those actually entered into the stepper. Using the modeled distortions obtained from the original data set as the `correct' values of overlay distortion present on the die/wafers, it was possible to model subsets of the original data set to determine the most efficient sample plans for manufacturing. The accuracy and uncertainty of the modeled overlay distortions was found to be dependent on the sample plan, both in terms of the number and location of measurements taken.
The steady state motion of a particle in a single wafer reactor is investigated by mathematical simulation. The goal is to determine the effects of the operating conditions on particle contamination. The flow simulations show that particle contamination during steady state processing (nonplasma) is small in single-wafer reactors running at moderate conditions. Steady state contamination of the wafers occurs when the particle momentum is large, due either to large particles or high velocities which can be from either high flow rates or low pressures. However, for low velocities and large residence times, gravity will cause particles to settle out of the flow. For this case, face-down processing has a large advantage over face- up. Thermophoretic forces are very important at low velocities. Hot surfaces remain clean, whereas cold surfaces become contaminated. Since steady state contamination is not very likely for small particles, contamination may arise from large particles that break up on impact or from nonsteady operation when the gases are turned on and off.
Experimental investigations into long term process variability at Digital's FAB4 facility indicated batch to batch changes in photochemicals were a significant contributor to process variation. The individual resist and developer batches themselves were within photospeed specifications: however, certain combinations of the two chemicals occasionally resulted in an out of spec condition. A study was undertaken to investigate this phenomenon. The work commenced with an extensive photospeed measurement capability study between the supplier and Digital. Upon completion of the capability work a statistically designed experiment was defined to investigate `system' photospeed. The experiment involved examining the resultant photospeed for all possible combinations of five individual resist and developer batches. Each resist and developer batch was manufactured to a unique photospeed target with values selected to cover and exceed the current photospeed specifications for each of the individual chemicals. The experimental results led to the development of a photochemical batch EO model which defined resultant photospeed as a function of the individual resist/developer batch photospeeds.
The major requirement for hot- and chill-plate designs is that they provide repeatable and uniform process conditions thereby assuring consistent photoresist quality. A collection of feature-based thermal models has been developed to predict temperature-time histories considering plate construction features including chuck heating/cooling methods, sensor placement with a PID control algorithm, and effects due to vacuum grooves, access holes, support pins and edge-gap. These models can be used by designers and process technologists to assess new approaches, optimize current design and set performance specifications.
Using a site services development spray monitor (DSM 100) and a post processing algorithm, the in-situ measured development rates of photoresist were obtained. The interference signals for eight different wavelengths were simultaneously monitored on a patterned wafer as it spun on the development module of a wafer track. Since the interference signal is generated from a circularly polarized light source, the DSM 100 has demonstrated robustness to the red cloud effect, developer spray, bubbles in the developer, and ambient light. After collecting the eight interference curves, these post processing algorithms used the Marquardt Levenberg non- linear regression algorithm and a linear regression approach to find the development rate as a function of development time. The first approach generated the better curve. A plot of development rate versus depth was generated via numerical integration of the plot of development rate versus time. This technique is equally well suited for other types of exposure and resist chemistries.
In order to truly represent photolithography through simulation, the exposure, bake, and development models and model parameters must be accurate. Using the approach for the measurement of the in-situ development rate, developed in the first paper of this two paper series, the model parameters were extracted for Shipley 812 resist with Shipley MF312 developer. Development rates for exposures of 66, 90, and 114 mJ/cm2 were measured. It was discovered that the set of Kim model parameters, R1 through R6, were highly correlated with the combination of the Dill exposure parameters. Thus, for A equals 0.581 micrometers -1, B equals 0.082 micrometers -1 equals 0.013 cm2/mJ, the parameters R1 equals 25.559 micrometers /min, R2 equals 10.451 micrometers /min, R3 equals 1.879, R4 equals 0.112, R5 equals 1.586, R6 equals 0.000 micrometers , and (sigma) equals 0.0016 micrometers were extracted. A comparison of simulated data using the extracted model parameters with the measured data demonstrated the quality of the fit.
Spectrophotometry has been applied to optimizing photolithography processes in semiconductor manufacturing. For many years thin film measurement systems have been used in manufacturing for controlling film deposition processes. The combination of film thickness mapping with photolithography modeling has expanded the applications of this technology. Experimental measurements of dose-to-clear, the minimum light exposure dose required to fully develop a photoresist, are described. It is shown how dose-to-clear and photoresist contrast may be determined rapidly and conveniently from measurements of a dose exposure matrix on a monitor wafer. Such experimental measurements may underestimate the dose-to- clear because of thickness variations of the photoresist and underlying layers on the product wafer. Online modeling of the photolithographic process together with film thickness maps of the entire wafer can overcome this problem. Such modeling also provides maps of dose-to- clear and resist linewidth that can be used to estimate and optimize yield.
In lithographic alignment, the previously etched features on the wafer are used for aligning the wafer with the mask for subsequent exposure steps. Accurate and timely estimation of the position of the alignment patterns on the wafer is becoming more crucial as feature sizes continue to shrink, and misalignment errors become less tolerable. In this paper, we propose a low complexity algorithm for estimating the position of the axis of symmetry of registration marks in lithographic alignment. The proposed technique is based on the exploitation of our recently developed SLIDE (subspace-based line detection) algorithm along with ideas from communication theory, and produces sub-pixel resolution estimates for the axis of symmetry of alignment marks. A further stage of the algorithm provides estimates of the linewidth.
This test structure is based on the voltage-dividing potentiometer principle and was originally replicated in a single lithography cycle to evaluate feature placement by a primary pattern generator. A new test structure has now been developed from the single-cycle version and has been used for measuring the overlay of features defined by two different exposures with a stepping projection aligner. The as-measured overlay values are processed by an algorithm that minimizes the effects of nominal random pattern imperfections. The algorithm further partitions measurements of overlay into contributions that derive, respectively, from misregistration of the image fields projected by the two masks and from the drawn misplacement of features on the masks. The numerical estimates of these contributions so obtained from the electrical measurements were compared with those extracted from the same features by the NIST line scale interferometer, providing traceability to absolute length standards. The two sets of measurements were found to agree to within the several-nanometer uncertainty cited for the line scale interferometer's readings alone.
Specific forced currents are required for different materials and feature sizes to ensure the best measurement precision and to minimize Joule heating. The determination of the optimum forced current depends on several parameters: sheet resistance, doping level, feature aspect ratio, and arm length/width of the van der Pauw (VDP) structure. A test of several different materials, resistivities, and feature sizes shows that the optimum forced current in the bridge and the VDP structures can be determined by simple empirical equations. The affect of Joule heating in a 0.2 micrometers structure was also evaluated. When supplied a forced current above the critical current density, the initial voltage reading is 9% larger than the initial voltage reading with the optimum forced current. There was no obvious Joule heating effect below the critical current density. In the extreme case an optimum forced current applied to a 0.22 micrometers structure for as long as 10 minutes produced a voltage rise exponentially to only 0.2% of the normalized voltage measured at the beginning.
As understanding of the effects of defects on reduction reticles advances, the desire for automatic detection of all classes of defects is created. The comprehensive detection of defects on reduction reticles is the ability to detect and classify defects that have not previously been associated with the defect inspection task. Test reticles have been fabricated with defects of these types and used to characterize inspection systems. Inspection characterization results show that a modified inspection system using simultaneous transmitted and reflected light inspection allows the detection of contamination on chrome and glass surfaces. Using an unmodified inspection system with standard defect detection algorithms, critical dimension errors due to e-beam lithography system butting errors were detected for errors smaller than 0.20 micrometers . Using an enhanced defect detection algorithm, transmission errors greater than -10% on contact geometry were detected.
Our goal for the CD metrology process is to understand the influence of defocus and illumination latitude upon measured CDs and to optimize the focus and illumination settings for smallest measured CD range. For consistent submicron optical metrology process, the measured CD range should be better than +/- 10 nm (6S). The defocus and illumination latitudes are generated when the features are measured through focus at different illuminations. The process step is the factor that sets the conditions for different illumination modes. Traditional illumination modes in mask metrology are transmitted and reflected. The confocal reflected illumination mode adds a new dimension to the standard reflected light because of the increase in both transversal and longitudinal resolutions. The combined illumination between transmitted and reflected confocal modes proposed here, provide increased feature edge gradient and decreased intensity background noise. To emphasize the effects of the illumination modes, an algorithm is developed for CD metrology optimization using traditional and combined illumination techniques.
A self-reference technique is developed for detecting the location of defects in repeated pattern wafers and masks with low-order distortions. If the patterns are located on a perfect rectangular grid, it is possible to estimate the period of repeated patterns in both directions and then produce a defect-free reference image for making comparison with the actual image. But in some applications, the repeated patterns are somehow shifted from their desired position on a rectangular grid, and the aforementioned algorithm can not be directly applied. In these situations, to produce a defect-free reference image and locate the defected cells, it is necessary to estimate the amount of misalignment of each cell beforehand. The proposed technique first estimates the misalignment of repeated patterns in each row and column. After estimating the location of all cells in the image, a defect-free reference image is generated by averaging over all the cells and is compared with the input image to localize the possible defects.
The printability of sub-micron 5X reticle defects at G-Line, I-Line, and DUV (248 nm) wavelengths is assessed by both practical experiment and computer simulation. The photoresist exposure and development parameters were measured, where necessary, and used for the modeling with the same specifically designed test reticle incorporating defects whose size, and proximity to adjacent features, varies within sub-micron line/space arrays. Results are presented by plotting minimum printed defect vs array linewidth for both adjacent and isolated defect sites. The resist modeling program SOLID has been used extensively, not only to simulate the practical work at all 3 wavelengths, but additionally to create a 3D representation of the effects caused by the printed defects. Results on defect printability enable future reticle procurement specifications to be established.
Conventional resist, without and with an underlying anti-reflective coating, and a dyed resist are used to calibrate the sub-micron dimensional control across a 6 inch diameter wafer coated with LPCVD polysilicon, as used in the manufacture of advanced CMOS devices by i-line technology. Results are referenced to the dimensional control measured for the same resist process on bare silicon test wafers. The effect of variable substrate reflectivity, with respect to the different resist processes, is thus assessed. Intra-field dimensional control over typical circuit topography is also measured for the same resist processes. Results are related to the amplitude of the linewidth vs resist thickness functions of the appropriate process that are derived from simulations using the SOLID modeling package.
The output signal from a multichannel plate detector (MCP) can be processed by one of two methods: pulse counting or charge accumulation. For a two-stage MCP, the output signal-to- noise ratio is nearly twice as great for pulse counting. This represents a significant advantage in low count-rate applications, such as e-beam metrology of non-conducting specimens.
We have initiated an effort to develop metrology tools that isolate the effect of each process step. Light scattered from diffracting structures is analyzed to determine characteristics of the structure. The technique is rapid, non-destructive, and extremely sensitive to variations in the samples that were examined. Through our technical collaboration with Texas Instruments Inc. we obtained wafers coated with surface imaging resists and exposed under varying focus and exposure conditions. We present results that utilize scatterometry to monitor the exposure step to determine defocus and exposure variations in the latent image. We also report using scatterometry to monitor the post-exposure bake (PEB) process for chemically amplified resists. Wafer-to-wafer variations in resist and underlying film thicknesses result in CD variations for constant exposure. The PEB time can be adjusted for each wafer to account for some of the parameter variations. We present experimental data supporting the concept of a scatterometer PEB monitor.
Scatterometry is shown to be a viable alternative to current methods of post-developed line shape metrology. Five wafers with focus-exposure matrices of line-space grating patterns in chemically amplified resist were generated. The gratings were illuminated with a He-Ne laser and, utilizing only the specular reflected order measured as a function of incident angle, we were able to predict linewidth and top and bottom rounded features. The scatterometry results were verified with those obtained from scanning electron microscopy (SEM). A set of wafers having a SRAM device pattern was analyzed. These wafers contain columns of devices, each having received an incremental exposure dose. We present exposure predictions based on data taken with the dome scatterometer, a novel device which measures all diffraction orders simultaneously by projecting them onto a diffuse hemispherical `dome.' A statistical calibration routine was used to train on the diffraction patterns from die locations with known exposure values.
In this paper we present the results of an evaluation into the effects of mask unflatness on the overlay budget. We have investigated two different situations: firstly the case of a single sided telecentric lens and secondly that of a double telecentric one. The results have been determined by measuring this effect directly on wafer.
The use of a diffraction-based latent image detector during the post-exposure bake (PEB) step for a chemically amplified resist system was investigated and its use in a feedback control strategy was examined. A calibration between intensity of light diffracted from the wafers during PEB and the final post-develop linewidth was determined. Using this relationship, two feedback control strategies were tested. One method altered the PEB time to compensate for unmeasured process disturbances and drive the linewidth to its target. The other method involved altering of the develop time. We found that using the post-exposure bake monitor in a feedback control system can improve wafer-to-wafer and lot-to-lot variability to below that which has been possible through conventional SEM measurements.
The stacked cell design of DRAM processes for lithography considerations has suffered severe topography step-height and unsmooth surface issues. In addition, the stability and uniformity control of thin film processes on the backend process can affect lithography process to a great extent. In this study, the AFM (atomic force microscope) has been used to study topography issues of a typical DRAM process. The detailed information concerning the topography step- height, flow angle, local unsmooth surface, etc., have been clearly identified. These studies provide useful information for future process development and improvement.
To facilitate the use of AFMs for manufacturing we have initiated a project to develop and calibrate artifacts which can in turn be used to calibrate a commercial AFM so that subsequent AFM measurement are accurate and traceable back to the wavelength of light. We plan to calibrate our artifacts using a specially designed AFM system which we call the Calibrated AFM (C-AFM). The C-AFM has been constructed as much as possible out of commercially available components. We use a flexure stage driven by piezoelectric transducers for scanning; a heterodyne interferometer to measure the X-Y position of the sample; a capacitance sensor to measure the Z position of the sample; and a commercially available AFM control system. The control system has two feedback loops which read from the X and Y interferometers, respectively, and adjust the piezoelectric voltages to keep the X-Y scan position accurate. The critical electromechanical and metrology issues involved in the construction and operation of such a system are discussed in detail.