Electrical test structure for overlay metrology referenced to absolute length standards

Michael W. Cresswell; William B. Penzes; Richard A. Allen; Loren W. Linholm; Colleen H. Ellenwood; E. Clayton Teague

doi:10.1117/12.174149

1 May 1994 Electrical test structure for overlay metrology referenced to absolute length standards

Michael W. Cresswell, William B. Penzes, Richard A. Allen, Loren W. Linholm, Colleen H. Ellenwood, E. Clayton Teague

Proceedings Volume 2196, Integrated Circuit Metrology, Inspection, and Process Control VIII; (1994) https://doi.org/10.1117/12.174149
Event: SPIE's 1994 Symposium on Microlithography, 1994, San Jose, CA, United States

Abstract

This test structure is based on the voltage-dividing potentiometer principle and was originally replicated in a single lithography cycle to evaluate feature placement by a primary pattern generator. A new test structure has now been developed from the single-cycle version and has been used for measuring the overlay of features defined by two different exposures with a stepping projection aligner. The as-measured overlay values are processed by an algorithm that minimizes the effects of nominal random pattern imperfections. The algorithm further partitions measurements of overlay into contributions that derive, respectively, from misregistration of the image fields projected by the two masks and from the drawn misplacement of features on the masks. The numerical estimates of these contributions so obtained from the electrical measurements were compared with those extracted from the same features by the NIST line scale interferometer, providing traceability to absolute length standards. The two sets of measurements were found to agree to within the several-nanometer uncertainty cited for the line scale interferometer's readings alone.

Citation Download Citation

Michael W. Cresswell, William B. Penzes, Richard A. Allen, Loren W. Linholm, Colleen H. Ellenwood, and E. Clayton Teague "Electrical test structure for overlay metrology referenced to absolute length standards", Proc. SPIE 2196, Integrated Circuit Metrology, Inspection, and Process Control VIII, (1 May 1994); https://doi.org/10.1117/12.174149

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