As the design rule of devices continues to shrink, the overlay margin of layer to layer continues to become smaller. Inter-field error of overlay can be compensated by alignment parameters of the exposure system, but intra-field error of overlay is very difficult to change within a field. This paper discusses the intra-field overlay error, especially that caused by oxidation and deposition processes of a metal-oxide-silicon (MOS) integrated circuit device. In an experiment, to analyze process induced affects on the intra-field overlay error of device, we monitored thermal process, film deposition, oxidation, lithography, etching, and implantation process and pursued the trend and sources of intra-field overlay error generated in wafer process. We analyzed the affects of film stress and thermal process by measuring box and box overlay marks using the KLA metrology system at the etch process step.