1 May 1994 Process-induced effects on the intrafield overlay error
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As the design rule of devices continues to shrink, the overlay margin of layer to layer continues to become smaller. Inter-field error of overlay can be compensated by alignment parameters of the exposure system, but intra-field error of overlay is very difficult to change within a field. This paper discusses the intra-field overlay error, especially that caused by oxidation and deposition processes of a metal-oxide-silicon (MOS) integrated circuit device. In an experiment, to analyze process induced affects on the intra-field overlay error of device, we monitored thermal process, film deposition, oxidation, lithography, etching, and implantation process and pursued the trend and sources of intra-field overlay error generated in wafer process. We analyzed the affects of film stress and thermal process by measuring box and box overlay marks using the KLA metrology system at the etch process step.
© (1994) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Young-Mog Ham, Young-Mog Ham, Chul-Seung Lee, Chul-Seung Lee, YoungSik Kim, YoungSik Kim, Dong-Jun Ahn, Dong-Jun Ahn, Soo-Han Choi, Soo-Han Choi, YeonSeon Seo, YeonSeon Seo, Mark Andrew Merrill, Mark Andrew Merrill, } "Process-induced effects on the intrafield overlay error", Proc. SPIE 2196, Integrated Circuit Metrology, Inspection, and Process Control VIII, (1 May 1994); doi: 10.1117/12.174138; https://doi.org/10.1117/12.174138

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