15 March 1994 Efficient systolic architecture for the one-dimensional wavelet transform
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Abstract
We present in this paper an architectural design for a wavelet transform chip for use in real-time one-dimensional signal processing applications. Based on the observation that further levels of the wavelet transform require only as much computation as the first level, our architecture requires only one row of processing elements to compute the complete transform. This is compared to previous designs requiring one row of processing elements per level of the transform. Our architecture provides the output of the transform in two forms, one with all levels multiplexed on one line (useful for transmission or compression) and the other as individual levels on separate lines synchronized in time to facilitate real-time analysis. We consider the usefulness of this architecture for real-time analysis of audio signals (typically 40kHz sampling rate) and discuss the design and implementation benefits of the computational simplicity of the presented architecture.
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Robert Lang, Erik Plesner, Heiko Schroder, Andrew Spray, "Efficient systolic architecture for the one-dimensional wavelet transform", Proc. SPIE 2242, Wavelet Applications, (15 March 1994); doi: 10.1117/12.170093; https://doi.org/10.1117/12.170093
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