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28 October 1994 Highly scalable hardware accelerator for digital signal processing
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In this paper, a highly scalable hardware accelerator design for digital signal processing is presented. The key features of this accelerator are minimum I/O operations, highly scalable massive parallelism, easy programming, and modularity and regularity. With a very large register file (> 1000) per processing element, the reuse factor per datum in this accelerator can be increased significantly (as compared to traditional DSP architectures). System performance is improved because the amount of data transfer between the on-chip cache and the off-chip cache/memory is reduced by the same factor. Since the basic building block of this accelerator is simply a VLSI chip with several processing elements, scalable massive parallelism can be achieved by connecting multiple chips together in a SIMD `vector- like' fashion. Finally, programming of this accelerometer is not difficult because it is operated under the SIMD `vector-like' mode. With the expected VLSI technology in the next few years, the throughput of one single accelerator chip can approach GFLOPs performance. Hence, the high computing power needed by digital signal processing applications can be provided by just connecting a small number of this chip together.
© (1994) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chi-Hung Chi and Siu-Chung Lau "Highly scalable hardware accelerator for digital signal processing", Proc. SPIE 2296, Advanced Signal Processing: Algorithms, Architectures, and Implementations V, (28 October 1994);


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