29 September 1994 Design and implementation of a polarization-controlled multistage interconnection network based on birefringent computer-generated holograms
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Abstract
There is a growing need in the telecommunication industry for a scalable switch that can provide high-throughput communication between a large number of I/O ports: a terabit switch. Recent advances in the area of fiber amplifiers has spurred interest in `transparent' optical networks, wherein communication between users is achieved without multiple conversions between the optical and electrical domains. Moreover, polarization compensators have been developed for single-mode fibers to allow automatic and stable control of the polarization stage of output optical signals. This may enable a polarization-independent switching system that uses polarization-dependent `all-optical' switches. Polarization switching has been widely proposed in the context of free-space optical multistage interconnection networks for switching applications as well as for multiprocessor interconnections. In this paper we suggest a novel polarization-controlled free-space optical switch and present the implementation and characterization of a 4 X 4 photonic switch. The switching system is based on a unique optical element capable of acting with an arbitrary independent phase function upon illumination with horizontally or vertically polarized monochromatic light. This element, known as a birefringent computer generated hologram (BCGH) is composed of two birefringent substrates, etched with a surface relief pattern and joined face to face. BCGH optical interconnects provide arbitrary independent, efficient responses to the two orthogonal linear polarizations, thereby reducing the number of optical components in the free-space optical system.
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Ashok V. Krishnamoorthy, Fang Xu, Joseph Earl Ford, Yeshaiahu Fainman, "Design and implementation of a polarization-controlled multistage interconnection network based on birefringent computer-generated holograms", Proc. SPIE 2297, Photonics for Processors, Neural Networks, and Memories II, (29 September 1994); doi: 10.1117/12.187305; https://doi.org/10.1117/12.187305
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