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11 October 1994 Synthesis of regular very large scale integration (VLSI) architectures for the 1D discrete wavelet transform
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Abstract
A methodology for synthesizing parallel computational structures has been applied to the Discrete Wavelet Transform algorithm. It is based on linear space-time mapping with constraint driven localization. The data dependence analysis, localization of global variables, and space-time mapping is presented, as well as one realization of a 3-octave systolic array. The DWT algorithm may not be described by a set of Uniform or Affine Recurrence Equations (UREs, AREs), thus it may not be efficiently mapped onto a regular array. However it is still possible to map the DWT algorithm to a systolic array with local communication links by using first a non-linear index space transformation. The array derived here has latency of 3M/2, where M is the input sequence length, and similar area requirements as solutions proposed elsewhere. In the general case of an arbitrary number of octaves, linear space-time mapping leads to inefficient arrays of long latency due to problems associated with multiprojection.
© (1994) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jose Fridman and Elias S. Manolakos "Synthesis of regular very large scale integration (VLSI) architectures for the 1D discrete wavelet transform", Proc. SPIE 2303, Wavelet Applications in Signal and Image Processing II, (11 October 1994); https://doi.org/10.1117/12.188779
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