16 September 1994 Architecture and modeling of a parallel digital processor based image processing system
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Proceedings Volume 2308, Visual Communications and Image Processing '94; (1994) https://doi.org/10.1117/12.185937
Event: Visual Communications and Image Processing '94, 1994, Chicago, IL, United States
Abstract
The paper describes an image processing system which uses both shared memory and message passing. Shared memory is used in conjunction with a high speed parallel bus to transfer image data; message passing is used for general inter-processor communication. A prototype system based upon the Texas Instruments TMS320C40 digital signal processor is currently in the final stages of construction. A Petri Net model of the communication aspects of the TMS320C40 processor has been developed. Features of the Petri Net software are discussed and the raw communication performance of the TMS320C40 shown. The modeling of a four and sixteen processor system applied to 2D FFT transforms is described.
© (1994) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
David Andrew Hartley, David Andrew Hartley, Shirish P. Kshirsagar, Shirish P. Kshirsagar, "Architecture and modeling of a parallel digital processor based image processing system", Proc. SPIE 2308, Visual Communications and Image Processing '94, (16 September 1994); doi: 10.1117/12.185937; https://doi.org/10.1117/12.185937
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