16 September 1994 Hierarchical heterogeneous multiprocessor system for real-time motion picture coding
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Proceedings Volume 2308, Visual Communications and Image Processing '94; (1994) https://doi.org/10.1117/12.185934
Event: Visual Communications and Image Processing '94, 1994, Chicago, IL, United States
Abstract
A multiprocessor system for high-speed processing of hybrid image coding algorithms such as H.261, MPEG or digital HDTV is presented in this study. Using a combination of a highly parallel 32-bit microprocessor and function specific devices controlled by microprogrammed controller, a new processing module is designed for a high performance coding system. In this study, we use 32-bit transputers for overall control and for operations requiring small amount of computation such as quantization, and function specific devices for repeated operation such as DCT and motion estimation. We constructed the motion picture coder using geometrical parallel processing techniques for inter processing module and algorithmic parallel processing for intra module since a single module alone cannot perform hybrid coding system algorithms at high speed.
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Sang Hoon Choi, Sang Hoon Choi, Choon Lee, Choon Lee, Young Gil Kim, Young Gil Kim, Seong Won Ryu, Seong Won Ryu, Kyu Tae Park, Kyu Tae Park, } "Hierarchical heterogeneous multiprocessor system for real-time motion picture coding", Proc. SPIE 2308, Visual Communications and Image Processing '94, (16 September 1994); doi: 10.1117/12.185934; https://doi.org/10.1117/12.185934
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