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16 September 1994 Low-power design of wavelet processors
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Proceedings Volume 2308, Visual Communications and Image Processing '94; (1994)
Event: Visual Communications and Image Processing '94, 1994, Chicago, IL, United States
This paper describes a VLSI architecture for low-power image compression applications. It implements a block-based wavelet transform with emphasis on minimal memory requirements, power consumption, and compression performance. The blocked transform partitions the original image into 16 X 16 data blocks with repeated boundary pixels for edge smoothing. Each block undergoes four octaves of 2D wavelet decomposition, and results in 13 subbands. The first octave uses Daubechies-4 transform, and the second, third, and fourth use Haar functions. The architecture consists of four 8-bit X 7-bit multiplier and accumulator units and one 13-bit adder. It implements 2D wavelet transforms directly with minimal memory and a small chip area. At 60 MHz, it processes a 512 X 512 gray-scale image in 23 ms and 18 ms for forward and inverse transforms respectively, satisfying the full-motion video requirement of 30 frames per second.
© (1994) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yi Kang, Belle W. Y. Wei, and Teresa H.-Y. Meng "Low-power design of wavelet processors", Proc. SPIE 2308, Visual Communications and Image Processing '94, (16 September 1994);

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