Memory failure analysis using EB voltage contrast image

Hiroyuki Hamada; Tohru Tsujide; Kazuo Nakaizumi

doi:10.1117/12.186751

14 September 1994 Memory failure analysis using EB voltage contrast image

Hiroyuki Hamada, Tohru Tsujide, Kazuo Nakaizumi

Proceedings Volume 2334, Microelectronics Manufacturability, Yield, and Reliability; (1994) https://doi.org/10.1117/12.186751
Event: Microelectronic Manufacturing, 1994, Austin, TX, United States

Abstract

This paper presents some novel fault localization techniques for a memory LSI by using an EB tester. Effective techniques for applying pulse combinations of input signals and acquiring images are put forward. Excellent voltage contrast images are acquired on the passivated devices without degradation of voltage contrast from charge up. Signal lines are back-traced by comparing good and bad images to identify the failure point. Application to the failure analysis of DRAMs is successfully performed with minimal time requirements.

Citation Download Citation

Hiroyuki Hamada, Tohru Tsujide, and Kazuo Nakaizumi "Memory failure analysis using EB voltage contrast image", Proc. SPIE 2334, Microelectronics Manufacturability, Yield, and Reliability, (14 September 1994); https://doi.org/10.1117/12.186751

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