14 September 1994 Plasma-induced gate oxide degradation and its impact on oxide reliability for CMOS FETs
Author Affiliations +
Plasma-induced gate oxide degradation has been investigated using CMOS device structures, as well as single-channel MOSFETs. The plasma process induces both interface states and oxide charges in n-ch and p-ch MOSFETs. Although forming gas anneal recovers or masks most of the damage, the damage reappears in the form of reduced hot carrier reliability. The study of dual-gate MOSFETs, in which an antenna aluminum-pad is shared by n-ch and p-ch MOSFETs, shows that the plasma charges collected by the antenna are equally divided between n-ch and p-ch MOSFETs. This indicates that the nature of the plasma stress acting on MOS devices is more like a current source. It was also found that a floating well structure used for CMOS does not protect MOSFETs from plasma damage.
© (1994) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ko Noguchi, Koichiro Okumura, "Plasma-induced gate oxide degradation and its impact on oxide reliability for CMOS FETs", Proc. SPIE 2334, Microelectronics Manufacturability, Yield, and Reliability, (14 September 1994); doi: 10.1117/12.186750; https://doi.org/10.1117/12.186750


Gate oxide damage and evaluation techniques
Proceedings of SPIE (April 16 1993)
Plasma-induced charging damage in P+-polysilicon PMOSFETs
Proceedings of SPIE (August 27 1997)
Novel AlCu: fill process for via applications
Proceedings of SPIE (September 04 1998)
Low-voltage CD-SEM applications in MEMS devices
Proceedings of SPIE (July 16 2002)

Back to Top