14 September 1994 Plasma-induced gate oxide degradation and its impact on oxide reliability for CMOS FETs
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Plasma-induced gate oxide degradation has been investigated using CMOS device structures, as well as single-channel MOSFETs. The plasma process induces both interface states and oxide charges in n-ch and p-ch MOSFETs. Although forming gas anneal recovers or masks most of the damage, the damage reappears in the form of reduced hot carrier reliability. The study of dual-gate MOSFETs, in which an antenna aluminum-pad is shared by n-ch and p-ch MOSFETs, shows that the plasma charges collected by the antenna are equally divided between n-ch and p-ch MOSFETs. This indicates that the nature of the plasma stress acting on MOS devices is more like a current source. It was also found that a floating well structure used for CMOS does not protect MOSFETs from plasma damage.
© (1994) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ko Noguchi, Ko Noguchi, Koichiro Okumura, Koichiro Okumura, } "Plasma-induced gate oxide degradation and its impact on oxide reliability for CMOS FETs", Proc. SPIE 2334, Microelectronics Manufacturability, Yield, and Reliability, (14 September 1994); doi: 10.1117/12.186750; https://doi.org/10.1117/12.186750


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