16 September 1994 Silicided versus nonsilicided gate technology for submicron CMOS ACIC applications
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Abstract
This study is a follow-up to earlier work comparing a 0.6 micron, 5 V silicided gate process to a non-silicided process including variations in 'wet' (delute steam) oxidation anneal conditions evaluated for process simplicity. The present data compares various 'dry' (oxygen only) anneal oxidation conditions with previously demonstrated baseline silicided and non-silicided (poly only) gate processes using combinations of nitrogen anneals and deposited oxides. The dry oxidation anneals prevented excessive gate oxide thickening at the gate edge found previously with wet oxidation. Dry oxidation led to minimal LDD overlap and minimal Idsat changes relative to either the silicided gate baseline or a non-silicided gate using thermal TEOS depositions and nitrogen anneals. Reliability data for the non-silicided dry oxidation anneals is included in this study. The non-silicided gate technology, either with dry oxidation anneals or with a deposited cap oxide gate structure and nitrogen anneals, produced hot-electron and gate oxide breakdown results comparable to the silicided gate baseline with potentially attractive manufacturing advantages.
© (1994) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Eric Johnson, Edward Nowak, Chung Wang, "Silicided versus nonsilicided gate technology for submicron CMOS ACIC applications", Proc. SPIE 2336, Manufacturing Process Control for Microelectronic Devices and Circuits, (16 September 1994); doi: 10.1117/12.186787; https://doi.org/10.1117/12.186787
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