3 October 1994 Defect pattern analysis and evaluation of printed circuit boards
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Proceedings Volume 2347, Machine Vision Applications, Architectures, and Systems Integration III; (1994) https://doi.org/10.1117/12.188732
Event: Photonics for Industrial Applications, 1994, Boston, MA, United States
Abstract
Recent manufacturing technologies require an automatic inspection system instead of human verification. This is true for the analysis of printed circuit boards with complex conductor patterns and fine pitches. This paper presents a methodology for an automatic inspection and an evaluation of printed circuit boards. We use here topological information on the conductors and insulators of boards. It incorporates a feature graph consisting of skeletons with several types of nodes and branches, locations and others. Inspection is performed by comparing the standard graph created from CAD data with the inspection graph of printed circuit boards. We will discuss fundamental but important preprocessing of optical image, optimum setting of necessary parameters for comparison, and a fast comparison method using variable-length inspection points.
© (1994) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Masayasu Ito, Masayasu Ito, Isao Fujita, Isao Fujita, Yoshinori Takeuchi, Yoshinori Takeuchi, } "Defect pattern analysis and evaluation of printed circuit boards", Proc. SPIE 2347, Machine Vision Applications, Architectures, and Systems Integration III, (3 October 1994); doi: 10.1117/12.188732; https://doi.org/10.1117/12.188732
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