5 April 1995 Optoelectronic interconnect architecture of parallel modified signed-digit adder and subtractor
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Proceedings Volume 2400, Optoelectronic Interconnects III; (1995); doi: 10.1117/12.206328
Event: Photonics West '95, 1995, San Jose, CA, United States
Abstract
In this paper, a space-position-logic-encoding scheme is proposed, which not only makes best use of the convenience of binary logic operation, but is also suitable for the trinary property of modified signed-digit numbers. Based on the space-position-logic-encoding scheme, a fully parallel modified signed-digit adder and subtracter is built by use of optoelectronic switch and microstructure interconnect technologies. Thus an effective combination of a parallel algorithm and a parallel architecture is implemented. Finally, both simulation results and experimental results are provided.
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
DeGui Sun, Na-Xin Wang, Li-Ming He, Zhao-Heng Weng, Daheng Wang, Ray T. Chen, "Optoelectronic interconnect architecture of parallel modified signed-digit adder and subtractor", Proc. SPIE 2400, Optoelectronic Interconnects III, (5 April 1995); doi: 10.1117/12.206328; https://doi.org/10.1117/12.206328
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KEYWORDS
Optoelectronics

Light emitting diodes

Binary data

Logic

Optical computing

Computer programming

Switches

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