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5 April 1995 Receiver design issues for parallel optical interconnections fabricated in the FET-SEED technology
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Abstract
This paper discusses the sensitivity limitations of smart pixel optical receiver arrays fabricated in the GaAs FET-SEED technology. Four circuit topologies (high impedance clamped, resistive load partially clamped, differential transamp, and common gate) are compared. Simulated and experimental data are presented.
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Robert A. Novotny, Anthony L. Lentine, Leo M. F. Chirovsky, and Ted K. Woodward "Receiver design issues for parallel optical interconnections fabricated in the FET-SEED technology", Proc. SPIE 2400, Optoelectronic Interconnects III, (5 April 1995); https://doi.org/10.1117/12.206320
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