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12 April 1995 Hardware architecture for rapid generation of electro-holographic fringe patterns
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Proceedings Volume 2406, Practical Holography IX; (1995)
Event: IS&T/SPIE's Symposium on Electronic Imaging: Science and Technology, 1995, San Jose, CA, United States
This report describe the hardware architecture and software implementation of a hologram computing system developed at the MIT Media Laboratory. The hologram computing employs specialized stream-processing hardware embedded in the Cheops Image Processing system--a compact, block data-flow parallel processor. A superposition stream processor performs weighted summations of arbitrary 1D basis functions. A two-step holographic computation method--called Hogel-Vector encoding--utilizes the stream processor's computational power. An array of encoded hogel vectors, generated from a 3D scene description, is rapidly decoded using the processor. The resulting 36-megabyte holographic pattern is transferred to frame- buffers and then fed to a real-time electro-holographic display, producing 3D holographic images. System performance is sufficient to generate an image volume approximately 100 mm per side in 3 seconds. The architecture is scalable over a limited range in both display size and computational power. The limitations on system scalability will be identified and solutions proposed.
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
John A. Watlington, Mark E. Lucente, Carlton J. Sparrell, V. Michael Bove Jr., and Ichiro Tamitani "Hardware architecture for rapid generation of electro-holographic fringe patterns", Proc. SPIE 2406, Practical Holography IX, (12 April 1995);

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