23 March 1995 Hierarchical multiprocessor-based image-analysis system
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Hierarchial structures permit distributed computing and multitasking for processing the partitionable image data. A two level hierarchial multiprocessor employing the 68000 master processor, three 8085 slave processors, shared memory mapping, VME backplane bus and dedicated operating system is presented in this paper. The task generation, scheduling and interprocessor communication is under OS control. Image processing algorithms like edge detection, segmentation, smoothing and compression were performed by the master and slaves simultaneously.
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
M. V. Raghunadh, M. V. Raghunadh, M. V.G.V. Prasad Babu, M. V.G.V. Prasad Babu, J. P. Raina, J. P. Raina, } "Hierarchical multiprocessor-based image-analysis system", Proc. SPIE 2421, Image and Video Processing III, (23 March 1995); doi: 10.1117/12.205489; https://doi.org/10.1117/12.205489


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