28 March 1995 High-speed low-power analog ASICs for a 3D neuroprocessor
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Abstract
A particularly challenging neural network application requiring high-speed and intensive image processing capability is target acquisition and discrimination. It requires spatio-temporal recognition of point and resolved targets at high speeds. A reconfigurable neural architecture may discriminate targets from clutter or classify targets once resolved. By mating a 64 X 64 pixel array infrared (IR) image sensor to a 3-D stack (cube) of 64 neural-net ICs along respective edges, every pixel would directly input to a neural network, thereby processing the information with full parallelism. However, the `cube' has to operate at 90 degree(s)K with < 250 nanoseconds signal processing speed and approximately 2 watts of power dissipation. Analog circuitry, where the spatially parallel input to the neural networks is also analog, would make this possible. Digital neural processing would require analog-to-digital converters on each IC, impractical with the power constraint. A versatile reconfigurable circuit is presented that offers a variety of neural architectures: multilayer perceptron, cascade backpropagation, and template matching with winner-take-all (WTA) circuitry. Special designs of analog neuron and synapse implemented in VLSI are presented which bear out high speed response both at room and low temperatures with synapse-neuron signal propagation times of approximately 100 ns.
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Tuan A. Duong, Tuan A. Duong, Sabrina E. Kemeny, Sabrina E. Kemeny, Mua D. Tran, Mua D. Tran, Taher Daud, Taher Daud, Anilkumar P. Thakoor, Anilkumar P. Thakoor, } "High-speed low-power analog ASICs for a 3D neuroprocessor", Proc. SPIE 2424, Nonlinear Image Processing VI, (28 March 1995); doi: 10.1117/12.205248; https://doi.org/10.1117/12.205248
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