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19 May 1995 Experimental x-ray process latitude evaluation using E-D tree analysis
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An E-D tree based analysis of experimental X-ray lithography data is presented for features characteristic of CMOS logic gate levels. Pattern-specific print biases for isolated lines (150- 250 nm) and two types of nested lines (250 nm) are characterized. Depths of gap for increasing exposure latitudes at +/- 20 nm line width control are calculated for individual features. common process window analysis is performed on the nested and isolated 250-nm patterns. The impact of reducing the nominal mask to wafer gap (35-26 micrometers ) on maximum exposure latitude is evaluated and the effect of gap reduction and overexposure on the nested to isolated print bias is examined.
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Lars W. Liebmann, Richard A. Ferguson, Ronald M. Martino, Angela C. Lamberti, J. F. Hart, and R. French "Experimental x-ray process latitude evaluation using E-D tree analysis", Proc. SPIE 2437, Electron-Beam, X-Ray, EUV, and Ion-Beam Submicrometer Lithographies for Manufacturing V, (19 May 1995);


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