22 May 1995 Monolithic delay lines with current-induced adjustment of the electrical parameters: new approach in design and metrology
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Abstract
A new approach in design and metrology of the monolithic delay line ICs with current-induced adjustment of the electrical parameters is proposed. The circuitry of the delay lines is based on using of two separate delay circuits for delay of the leading and trailing edges. In order to ensure the accuracy of the delay time the phenomenon of current-induced resistance change in polysilicon resistors is used. The measurement and adjustment of the dynamic parameters of the ICs are made on the silicon wafer directly after fabrication before packaging. The program algorithm and specially software and hardware method of the delay time measurement are presented. The main electrical parameters and fabrication costs of the designed monolithic delay line ICs are compared with the known monolithic delay line series.
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Nickolay G. Melentyev, "Monolithic delay lines with current-induced adjustment of the electrical parameters: new approach in design and metrology", Proc. SPIE 2439, Integrated Circuit Metrology, Inspection, and Process Control IX, (22 May 1995); doi: 10.1117/12.209208; https://doi.org/10.1117/12.209208
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