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26 May 1995 Reduction of ASIC gate-level line-end shortening by mask compensation
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Abstract
One of the most dramatic effects that one encounters when attempting the optical imaging of 0.5 k ASIC gate levels is the truncation or shortening of transistor geometries. This reduces the wafer process latitude and in some cases even eliminates the level-to-level overlay margin. We investigate a number of techniques, including various complexities of mask compensation and modified illumination to mitigate this phenomenon in manners sufficiently general to accommodate ASIC layouts.
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Joseph G. Garofalo, John DeMarco, J. Bailey, Jiabei Xiao, and Sheila Vaidya "Reduction of ASIC gate-level line-end shortening by mask compensation", Proc. SPIE 2440, Optical/Laser Microlithography VIII, (26 May 1995); https://doi.org/10.1117/12.209250
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