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17 February 1995 Silicon-based phased locked loop (PLL) clock recovery to regenerate 2.5-Gbit/s NRZ data
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Proceedings Volume 2450, Broadband Networks: Strategies and Technologies; (1995)
Event: Advanced Networks and Services, 1995, Amsterdam, Netherlands
This paper describes a board-level realization of 2.5 Gb/s clock and data regenerator circuit, where the clock recovery function is implemented by a phase locked loop configuration. In order to use a low cost commercially available voltage controlled oscillator (VCO) a Richman quadricorrelator frequency-difference discriminator has been designed. The resultant frequency and phase locked loop (FPLL), makes possible the frequency acquisition even if the VCO starting frequency were out of the PLL pull-in range. All components used are cheap commercially available silicon devices. Measurements, at 10-9 bit error rate, give an input electrical sensitivity less of 5 mVpp with 223-1 pseudo-random input data stream. The recovered clock jitter is compliant with SONET STM-16.
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Andrea Pallotta "Silicon-based phased locked loop (PLL) clock recovery to regenerate 2.5-Gbit/s NRZ data", Proc. SPIE 2450, Broadband Networks: Strategies and Technologies, (17 February 1995);

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