30 June 1995 System integration issues for high-speed parallel fiber optic interconnects
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In November 1994, the Optoelectronics Technology Consortium (OETC) demonstrated a working 32-channel bus with data transmission rates of up to 622 Mbps per channel and bit error rates of better than 8 X 10-15. The optoelectronic data bus provides a parallel, 32- channel, high-density (140 micrometers pitch), point-to-point, connection using existing GaAs IC, silicon optical bench (SiOB), and multichip module (MCM) technologies. In the course of developing the data bus, a number of integration issues arose that required the specialized talents of a team of individuals with diverse expertise. These individuals were located in at least four different geographical areas and were employees of four separate companies that had come together in a precompetitive industrial alliance. Communication between the team members was paramount in preventing design details from becoming serious integration issues. This paper will briefly describe some of the OETC data bus system integration issues encountered and them summarize the technical results.
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Booker H. Tyrone, Booker H. Tyrone, David Dening, David Dening, } "System integration issues for high-speed parallel fiber optic interconnects", Proc. SPIE 2481, Photonic Device Engineering for Dual-Use Applications, (30 June 1995); doi: 10.1117/12.212729; https://doi.org/10.1117/12.212729

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