New VLSI architecture for velocity computation of multiple moving objects in images

Chang-Yu Chen; Chin-Liang Wang

doi:10.1117/12.206653

21 April 1995 New VLSI architecture for velocity computation of multiple moving objects in images

Chang-Yu Chen; Chin-Liang Wang

Author Affiliations +

Proceedings Volume 2501, Visual Communications and Image Processing '95; (1995) https://doi.org/10.1117/12.206653
Event: Visual Communications and Image Processing '95, 1995, Taipei, Taiwan

Abstract

This paper presents a new systolic realization of the Fourier-based method for motion detection and velocity computation of multiple moving objects in images. In the architecture, the 2D discrete Fourier transform is computed via the 2D discrete Hartley transform (DHT) that involves only real valued arithmetic. The 2D DHT is realized based on the row-column decomposition without matrix transposition problems. The systolic system possesses the desirable features of regularity, modularity, and concurrency for VLSI implementation. It has a utilization efficiency of Min(N, M)/Max(N,M) X 100 percent and a throughput rate of one velocity estimation per T X Max(N,M) cycles, where N and M are the number of pixels of an image in the x- and y- directions, respectively, and T is the number of frames in the image sequence.

Citation Download Citation

Chang-Yu Chen, Chang-Yu Chen, Chin-Liang Wang, Chin-Liang Wang, } "New VLSI architecture for velocity computation of multiple moving objects in images", Proc. SPIE 2501, Visual Communications and Image Processing '95, (21 April 1995); doi: 10.1117/12.206653; https://doi.org/10.1117/12.206653

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