21 April 1995 Very large scale integration (VLSI) architectures for video signal processing
Author Affiliations +
Proceedings Volume 2501, Visual Communications and Image Processing '95; (1995) https://doi.org/10.1117/12.206782
Event: Visual Communications and Image Processing '95, 1995, Taipei, Taiwan
The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO, focussing on programmable architectures. Programmable video signal processors are classified and specified as homogeneous and heterogeneous processor architectures. Architectures are presented for reported design examples for the literature. Heterogenous processors outperform homogeneous processors because of adaptation to the requirements of special subtasks by dedicated modules. The majority of heterogenous processors incorporate dedicated modules for high performance subtasks of high regularity as DCT and block matching. By normalization to a fictive 1.0 micron CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicated a figure of merit for silicon efficiency.
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Peter Pirsch, Peter Pirsch, Winfried Gehrke, Winfried Gehrke, } "Very large scale integration (VLSI) architectures for video signal processing", Proc. SPIE 2501, Visual Communications and Image Processing '95, (21 April 1995); doi: 10.1117/12.206782; https://doi.org/10.1117/12.206782


HDR compression in the JVET codec
Proceedings of SPIE (September 17 2018)
Design Of A Freeze-Frame Coder
Proceedings of SPIE (June 03 1987)
VVD: VCR operations for video on demand
Proceedings of SPIE (November 22 1999)
An enhancement of H.264 coding mode for R D optimization...
Proceedings of SPIE (January 18 2010)

Back to Top