Very large scale integration (VLSI) implementation of block-based predictive Rice codec

Chien-Min Huang; Alan W. Shaw; Richard W. Harris

doi:10.1117/12.206744

21 April 1995 Very large scale integration (VLSI) implementation of block-based predictive Rice codec

Chien-Min Huang, Alan W. Shaw, Richard W. Harris

Proceedings Volume 2501, Visual Communications and Image Processing '95; (1995) https://doi.org/10.1117/12.206744
Event: Visual Communications and Image Processing '95, 1995, Taipei, Taiwan

Abstract

This paper presents a VLSI implementation of the lossless block-based predictive Rice codec (BPRC). The BPRC uses an adaptive predictive coding algorithm to remove the redundancy in the image, codes the residue using an entropy coder. This algorithm can adapt well to local images statistics. The codec chip will encode 4 to 16-bit pixels at 10 Mpixels/sec input, and decode at 10 Mpixels/sec output. For images of normal size it requires little supports circuitry, only input data formatting and output data defomatting. Large images can be supported with external FIFOs.

Citation Download Citation

Chien-Min Huang, Alan W. Shaw, and Richard W. Harris "Very large scale integration (VLSI) implementation of block-based predictive Rice codec", Proc. SPIE 2501, Visual Communications and Image Processing '95, (21 April 1995); https://doi.org/10.1117/12.206744

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