19 September 1995 Reconfigurable processor for a data-flow video processing system
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Abstract
The Cheops system is a compact, modular platform developed at the MIT Media Laboratory for acquisition, processing, and display of digital video sequences and model-based representations of moving scenes, and is intended as both a laboratory tool and a prototype architecture for future programmable video decoders. Rather than using a set of basic, computationally intensive stream operations that may be performed in parallel and embodies them in specialized hardware. However, Cheops incurs a substantial performance degradation when executing operations for which no specialized processor exists. We have designed a new reconfigurable processor that combines the speed of special purpose stream processors with the flexibility of general-purpose computing as a solution to the problem. Two SRAM based field-programmable gate arrays are used in conjunction with a Power PC 603 processor to provide a flexible computational substrate, which allows algorithms to be mapped to a combination of software and dedicated hardware within the data-flow paradigm. We review the Cheops system architecture, describe the hardware design of the reconfigurable processor, explain the software environment developed to allow dynamic reconfiguration of the device, and report on its performance.
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Edward K. Acosta, Edward K. Acosta, V. Michael Bove, V. Michael Bove, John A. Watlington, John A. Watlington, Ross A. Yu, Ross A. Yu, } "Reconfigurable processor for a data-flow video processing system", Proc. SPIE 2607, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, (19 September 1995); doi: 10.1117/12.221348; https://doi.org/10.1117/12.221348
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