The main benefit of the throughput improvement that is possible to achieve with link rates of Gb/s in ATM is the exploitation of statistical gain with bursty high peak rate sources. But not only statistical gain justifies the necessity for such advanced technology. High speed ATM switching systems take advantage of the reduction of the number of interface devices (due to multiplexing) and also the number of stages in the ATM switching network, obtaining better figures in the cost/performance ratio. This paper evaluates the network efficiency improvement by using statistical gain and its describes an ATM switch that exploits parallelism and segmentation to perform very high speed ATM switching. With this characteristic it is possible to switch more than 2.5 Gb/s per input/output using CMOS and BiCMOS technologies.