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22 September 1995 Manufacturing reliability and yield optimization of GaAs MMICs
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Improving yield and reliability while reducing fabrication cost is a constant challenge in the semiconductor industry; in this context, while evaluating new fabrication equipment for a 3 inch fabline, unexpected physical defects occurred during reliability test at elevated temperature (300 degree(s)C): they consisted in a degradation of the 2nd TiPtAu interconnect level, accompanied by localized cracks and peel-off of the final SiN passivation layer. This paper describes the work undertaken to find out the origin of the observed defects, to set proper process conditions and to optimize the process. Design of experiments (DOE) has been used to find out that a SiO2 isolation layer was responsible for the occurrence of the observed defects. Then, it has also been used to model the effect of the deposition parameters as a function of the main properties of this isolation layer: uniformity, internal stress, deposition rate, etch rate in aqueous solution, refractive index, and of course generation of the above mentioned defects. Finally, making use of the model, we have achieved the optimization of the PECVD process with the following constraints: total disappearance of the mentioned defects, including reliability tests at elevated temperature, minimum internal stress of the layer compatible with best uniformity and dielectric density. The new deposition conditions have been validated through electrical measurements made on metal-insulator-metal capacitances before and after reliability test performed at elevated temperature (300 degree(s)C).
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Andre Mitonneau, Edwige Guillemet, Jean-Louis Deviller, and Pierre Baudet "Manufacturing reliability and yield optimization of GaAs MMICs", Proc. SPIE 2635, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis, (22 September 1995);

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