22 September 1995 Yield improvement by wafer edge engineering
Author Affiliations +
Improvements in defect reduction of semiconductor processes and equipment have realized higher wafer sorts yield but have typically limited analysis and inspection of the edge of wafers by several millimeters. Sort yield on production wafers has been observed to be reduced by glass flaking and other undesired structures created on wafer edges which defect inspection typically excludes and process equipment overlooks their effect. We have taken a systematic approach to characterize integrated wafer edge processing such as size and tolerance of clamping during film deposition and plasma etching. Characterization of wafer edge processing is further refined through the use of process simulations. This modeling allows for predictive effects of changes in edge schemes as well as effects of gradual process equipment deviations such as varying clamp size during target lifetime in PVD equipment. By characterizing and modeling wafer edge processing we are able to circumvent defects that are generated by processing conditions unlike what is called for by design rules.
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Fred N. Hause, Fred N. Hause, Daniel Kadoch, Daniel Kadoch, Dilip Wadhwani, Dilip Wadhwani, "Yield improvement by wafer edge engineering", Proc. SPIE 2635, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis, (22 September 1995); doi: 10.1117/12.221443; https://doi.org/10.1117/12.221443


Wafer-cleaning process after plasma metal etch
Proceedings of SPIE (July 06 1997)
Defect reduction strategy for plasma etch
Proceedings of SPIE (August 26 1999)
Correction for etch proximity: new models and applications
Proceedings of SPIE (September 13 2001)
On-line optimization of stop-etch time
Proceedings of SPIE (February 14 1994)

Back to Top