High throughput and low cost production with 100% yield is strictly demanded for ULSI manufacturing, where a decrease of minimum feature size of device and an increase of wafer diameter are continuously enhanced for future. It will be available based on an introduction of simplified processing due to simplified device structure by introducing new concept device and new materials to Si technology. Simplification of manufacturing process becomes available based on fully understanding of process mechanisms in a scientific manner, resulting in a dramatic reduction of process steps.

As device dimensions become scaled to the deep sub-micron regime, the field oxidation process is most significant in achieving reliable oxide quality in gate and LOCOS edge regions. Overall, the role of the field oxide must be to provide excellent isolation and to remain reliable at the LOCOS edge and have minimum encroachment.

The purpose of this work was to investigate the latch-up temperature dependence of majority carrier guard structures with the goal to find design rules for latch-up free high temperature operation of a CMOS- ASIC. Measurements up to 250 degree(s)C show an enhanced latch-up resistance of majority carrier guards compared to conventional electrode placement. With increasing temperature holding voltage and current decrease for both types. The test devices have also been simulated using 2D FEM device simulation. For majority carrier guard structures it is essential to use Fermi-Dirac-statistics instead of Boltzmann-statistics and a mobility model which accounts for carrier-carrier scattering in order to get accurate simulation results. In a further step the simulations were used to predict the necessary guard width for holding voltages higher than 5V to gain absolutely latch-up free operation at 250 degree(s)C. The results can be exploited for the design of temperature resistant, latch- up free CMOS circuits. The work is relevant for an ongoing effort to make use of junction isolated CMOS technology for temperature resistant electronics up to 250 degree(s)C.

Inductively Coupled Plasma (ICP) and diode sputter etch processes for via filling technology were evaluated in view of the plasma and/or high field damage to the 7 nm gate oxide in both n- and p-channel MOSFETs using 0.35 micrometers CMOS technology. A number of sputter process conditions were considered including the substrate bias, gas flow, and sputter power to examine the threshold voltage instability, drive currents degradation and charge trapping in the gate oxide and the generation of Si/SiO₂ interface traps. Via sizes ranging from 0.5 to 1.0 micrometers were studied for lower and tighter distributions of via resistance. A comparison between ICP and diode sputter processes showed better process robustness for ICP sputter etch than of the diode sputter process. Un- annealed and as processed devices showed as high as 20% change in threshold voltage (V_t) shift and 10% decrease in drive currents for the diode sputter process while the ICP process resulted in as low as 5% change in threshold voltage shift and less than 3% degradation in drive currents. Differences between n- and p-MOSFETs degradation were also observed. The possible process-induced device damage mechanisms will be discussed.

High speed and high performance is essentially required in CMOS ULSI of super workstations in the 21st century's multimedia era with every possible means. Low temperature operation of CMOS ULSI should be re- recognized for high speed application, because the low-temperature operation can always exhibit 2-3 times higher operation speed than room- temperature operation when the same design-rule microfabrication process is utilized. In this paper, we discuss a temperature scaling theory (TST) and temperature-dimension combination scaling theory (CST) for 0.1 micrometers and below-0.1 micrometers MOSFET. Emphasis of the combination scaling is that the threshold voltage and the subthreshold swing are fully scaled for low-supply voltage operation. The fabricated 77K CST-MOSFET with 1-V supply voltage has the threshold voltage (V_th) of 0.21 V and the subthreshold swing (S) of 27 mV/dec without degradation of V_th and S due to the short-channel effects.

We demonstrated a CMOS invertor with a 15 ps propagation delay (t_pd) at 77 K. This device uses n⁺ - p⁺ double-gate SOI MOSFETs with a gate length (L_G) of 0.19 micrometers and a gate oxide thickness (t_ox) around 9 nm. The channel doping concentration of this device is maintained as low as 10¹⁵ cm^-3 even in the deep submicron gate length regime while maintaining short channel immunity. Therefore, the decreased phonon scattering due to the cryogenic operation causes a significant increase in mobility, which leads to smaller t_pd than any other reported values for a given L_G. Although the threshold voltage (V_th) increases with a decrease in temperature, we can adjust it for cryogenic operation by controlling t_ox and the SOI thicknesses (t_Si).

A fundamental limit to the scaling of CMOS supply voltages (V_CC) exists due to the statistical variation of MOSFET threshold voltage (V_T). At the microscopic (device-to-device) level, an inherent variability in V_T exists due to the randomness of the number of dopants in the depletion region of the MOSFET. As the number of dopants in the depletion region decreases with scaling, the V_T variations will increase and become more significant. In addition to this fundamental variation in V_T, systematic V_T variations exist due to manufacturing fluctuations with the gate length, gate oxide thickness, implant uniformity, and anneal temperatures. For SRAM circuits, the V_T mismatch caused by channel dopant fluctuations degrades the cell stability and limits the minimum operating voltage of the SRAM. For logic circuits, the systematic V_T variations across a waver significantly increase the variation of the measured propagation delay on a wafer as V_CC is scaled down towards the MOSFET V_T. These limitations on V_CC scaling pose additional challenges in the design and manufacturing of devices and circuits for low-power systems.

The paper presents a novel PNP-type BJT-mode operated MOS structure that significantly pushes up the cut-off frequency limit, without necessarily employing submicron patterning. In order to reach the requested high speed, the base width (channel length) is rendered independent of processes minimum feature and the excess minority carriers charge in the extrinsic base is reduced using an insulation technique. Full bulk hole mobility is obtained by operating the MOS structure in 'purely BJT- mode'. The proposed device is fully compatible with standard recessed LOCOS single-polysilicon BiCMOS processes and offers a valid alternative to shallow polysilicon emitter vertical PNP-type transistors. Our CAD simulations yielded maximum cut-off frequencies of 2.45 GHz, 3.05 GHz and 5.65 GHz for 2 micrometers , 1 micrometers and 0.4 micrometers minimum feature structures, respectively.

For the design of a scaled CMOS technology, it becomes necessary to use predictive device simulation to improve MOSFET design and reduce the design cycle time. The results of a simulation study which is carried out to predict the performance of N and P channel MOSFETs with a physical gate length (L_g) of 0.18 micrometers are reported in this paper. The performance of the MOSFETs is estimated using a performance Figure of Merit (FOM[1]) calculated from their simulated I-V characteristics. This study is used to identify particular improvements to an existing 0.25 micrometers , 2.5 V, 60 A technology [2] so as to meet the FOM target at a 0.18 micrometers , 1.5 V, 36 A technology node.

A cost-effective CMOS LDD process is described. This process, if single polysilicon and single metal, uses total of only seven masking steps: well, isolation, gate, source/drain, contact, metal, and passivation. Main strategy of the process is to implant blanket for one type of doping regions and compensated with masked implants for the other type. In our embodiment, blanket n-well is formed by implant and high- temperature drive-in before LOCOS isolation. Masked retrograde p-well is formed with multiple implants after LOCOS in order to fulfill different doping requirements for channel and field regions at one masking step. After gate definition, blanket n-LDD implant is performed, followed by side-wall spacer formation and blanket n+ source/drain implant. With p+ mask, three processing steps are performed: p+ source/drain implant, spacer removal and p-LDD implant. Finally, contact formation, metalization and passivation complete the process. The device parameters such as minimum gate length, VT, isolation, etc. are kept unchanged, compared to those of original non-compensated doping process. Some resistances and capacitances increase 20%.

This paper presents an improved figure-of-merit (FOM) for CMOS performance which includes the effect of gate resistance. Performance degradation due to resistive polysilicon gates is modeled as an additional delay proportional to the RC product of a polysilicon line. The new FOM is verified from delay measurements on inverter chains fabricated using a 0.25 micrometers CMOS process. A furnace TiSi₂ process is used to underscore the effect of increased sheet resistance of narrow polysilicon lines. Excellent correlation between measured and predicted inverter chain delays is obtained over a variety of design, process and bias conditions. An expression for the gate sheet requirement is derived from the new FOM. Using this expression requirements on the gate sheet are calculated corresponding to a technology roadmap for performance and oxide thickness.

When threshold voltage of CMOS-cell is corrected by low-dose ion- implantation method a shallow p-n junction is formed near oxide- semiconductor interface with junction depth approximately equal to Debye length. Known methods of electro-physical parameters control by C-V characteristic cannot be applied for these MOS structures directly. So, for the task of the determination of electro-physical parameters and doping profile in nonuniform substrate MOS structure the numerical solution of Poisson equation is commonly used. The approach to the designing of a low frequency C-V characteristic is considered in this paper for MOS structures with substrate doping impurity of different types. The mathematical model is based on approximate solution of Poisson equation and takes into account the majority and minority carriers. This model can be simply tune for any modeling impurity profile and allows to extract parameters such as dose of the implanted impurity, substrate impurity concentration, p-n junction depth, effective flat-band voltage, oxide charge density, oxide thickness, profile doping parameters. The cases of abrupt and gradual impurity distribution were considered. The parameters of MOS structure and impurities profile for different doping doses were extracted from experimental C-V curves. The comparison of experimental and modeling C-V characteristics shows good agreement (5-10%).

This paper presents a newly developed process technology to integrate the Ba_xSr_1-xTiO₃(BST) thin film prepared by an rf magnetron sputtering. Evaluations of the integrated BST capacitors on a test element group (TEG) structure revealed some of key issues for a successful integration. A two-step sputtering method comprising the first step to form a nucleation layer and the second step to form the main part of the BST film was found to be useful for preventing the dielectric properties of the integrated BST thin film from the degradation. A careful control of the shape of the lower structures such as the edge of the bottom electrode or the poly Si plug of the storage node turned to be indispensable to obtain the reliable capacitor and this recommends the extensive use of the process that can provide a flush surface such as the Chemical Mechanical Polishing (CMP) in the future integration. The interlevel dielectrics over the BST capacitor was shown to seriously affect the leakage characteristics and an undoped SiO₂ film was most suitable for the integrity, implying the needs for another planarization technique instead of the glass reflow. Finally, a preliminary evaluation of the reliability and the normal bit function of a 4 Mbits DRAM, made of fully flat BST stacked capacitors, demonstrated the utility of the developed integration technology.

In order to satisfy the twin requirements of increased performance at low cost, a novel architecture that allows the differentiation of the source and drain implants of an EPROM cell without any additional processing steps has been developed. This cell is more immune to electrical stress than a standard cell during both programming and read cycles. In addition, this cell is inherently electrically shorter and therefore can be used to reduce die size in advanced EPROM devices.

Memory repair through the use of laser processing of redundant elements is an industry standard procedure for memory chip manufacturing. But, shrinking memory feature sizes and the industry's tendency to use metals as link materials rather than polysilicon imposes new challenges for laser processing. So far, the majority of the research on memory link laser processing has concentrated on: The vertical structure of a link (such as the multiple layers of passivation, link, field oxidation and silicon substrate); the laser beam absorption; and, the different temperature distribution within the structure as the result of laser beam heating. Until now, the emphasis in laser link processing optimization has been aimed at creating uniform temperature distribution while severing the link before exploding the passivation layer. Our study has shown that the link width plays an important roll in the processing as well. Analysis of the mechanical stress beneath the passivation layer using finite element modeling has been carried out. Different link width and passivation layer thicknesses vary the stress dramatically. The results of this simulation will be presented and their implication on link processing optimization will be discussed. To optimize the laser processing further, we have proven that absorption contrast of laser energy between the link material and the silicon substrate beneath the link must be maximized. Based upon the fact that while the absorption of most metal materials in the 1.3- to 2-micron range remains the same as that at 1 micron, it drops dramatically for silicon. By using laser wavelengths within the 1.3- to 2-micron range, a much wider laser processing window can be realized. Comparison analysis of link processing by different laser wavelengths will be discussed.

This paper reports on the integrity of thin N₂O oxides in tungsten polycide (poly-Si/WSi₂ stack) gated MOS structures, which was characterized by their charge-to-breakdown (Q_BD). In this study, WSi₂ films were formed either by chemical vapor deposition (CVD) or sputtering. It is found that with CVD-WSi₂ gate, N₂O gate oxide has a much degraded integrity in terms of high infant-mortality rate and low Q_BD values compared with the sputtered WSi₂ gate.

The behavior of the MOS-structure composed of TiN_x/TiSi_y upper layer, 3500 angstrom thick LPCVD poly-Si layer, 200-300 angstrom thick thermal oxide grown on p-Si substrate were studied at various conditions of the fabrication process. The TiN_x/TiSi_y layer was formed by rapid thermal annealing (RTA) of the 200 angstrom thick titanium film previously sputter deposited on the poly-Si in nitrogen contained ambient. Samples with different compositions were obtained by varying the nitrogen content between 0% and 25% in Ar + N₂ mixture. Cross-section transmission electron microscopy (TEM) investigation show the silicide/poly-Si interface roughness appears to be smaller when nitrogen content increases in the Ar + N₂ working gas. TEM studies of the surface morphology reveal adding of nitrogen to the working gas yield a decrease in grain size of the film up to two-tree times if it reaches an upper limit. Measurements of sheet resistance of the titanium silicide/nitride layer displays these observations. In order to check how the process of formation of the upper layer influences the MOS-structure performances electrophysical measurements were taken. They show a decrease of instability of the work function ((Phi) _ms) values as well as negligible rize of interface state density when sintering of the silicide layer is carried out in nitrogen contained ambient. Fowler-Nordheim electron injection experiments demonstrate some increase of defects density in oxide at heat treatment at higher temperatures.

Scaling down of the tunnel oxides allows reduction of the internal programming voltages and the memory cell size, and simplification of the peripheral circuit design related to highvoltage operation. However, several serious factors limit the scaling down of conventional thermal oxides. This includes the reduction in endurance which is related to charge trapping and time-dependent dielectric breakdown of the tunnel oxide. Leakage currents such as stressinduced leakage current and direct tunneling current are becoming a dominant factor as thicknesses are scaled down. Other factors that might limit the scaling of conventional thermally grown oxides include high defect and pinhole density which affect the manufacturing yield and device reliability, the ineffectiveness of thermal oxides in blocking diffusion of dopants, metals and impurities, excessive interface state density generation under various types of electrical and radiation stresses, and inadequate charge-to-breakdown and time-to-breakdown values. Furthermore, it has been reported that post-oxidation processes such as plasma exposure during metal etching can degrade thin oxides.

This paper studies the hot-carrier immunity on the MOSFET analog performance with NO-nitrided SiO₂ gate dielectrics. Degradation due to hot-carrier stress was investigated in terms of several key analog parameters, including drain output resistance (R_o), voltage swing (V_swing), voltage gain (G_m(DOT)R_o), and differential offset voltage (V_offset). Results indicate that, as compared to conventional SiO₂, NO-nitrided SiO₂ significantly suppresses the hot-carrier degradation in analog device performance for both n- and p- MOSFETs. It is concluded that NO nitridation, which improves interface endurance and electron trapping characteristics of SiO₂ gate oxides, is a promising technique for analog CMOS applications.

In this paper, the in-situ rapid-thermal multiprocessing has been applied to fabricate high quality ultra thin dielectrics for various ULSI applications. An in-situ low pressure rapid-thermal reoxidation of Si₃N₄ films in N₂O ambient (LRTNO) has been demonstrated to realize high quality ultra thin (< 30 angstrom) ON stacked layers for DRAM applications. While the use of RTN provides a defect-free surface by eliminating interfacial native oxide and forming a very thin thermal nitride layer, the use of low pressure reoxidation suppresses severe oxidation of nitride film and the use of N₂O-reoxidation improves the quality of ON stacked layer. The resulting ON stacked layers through in-situ multiprocessing exhibit excellent electrical properties and reliability. A novel ultra thin ONO stacked films have been fabricated by combining the bottom and top N₂O-oxide layers with the ultra thin CVD-nitride layers for CMOS logic gate applications. The novel ONO structure is found to have good interfacial characteristics, reduced charge trapping and improved defect density. In addition, an excellent resistance to boron penetration is achieved mainly due to the good diffusion barrier property of the nitride layer. Results also show that the MOSFETs using this ONO structure have comparable initial electrical characteristic as those with control oxides and significantly enhanced hot-carrier immunity than both O₂ reoxidized ONO structure and control oxide.

In this paper, we have systematically investigated the effects of NH₃ nitridation of N₂O oxides and subsequent reoxidation on MOSFET performance and reliability. Results indicate that as compared to oxides grown in pure O₂ or N₂O ambient, NH₃ nitridation of N₂O oxides (with or without reoxidation) slightly degrades the electron mobility ((mu) _e,eff) of n-MOSFETs at low V_G, but enhances (mu) _e,eff significantly at high V_G. For p-MOSFETs, nitridation of N₂O oxides degrades hole mobility ((mu) _h,eff) slightly for all V_G. In addition, reoxidation of NH₃-nitrided N₂O oxides is required to improve the hot-carrier immunity for both n- and p-MOSFETs under various static bias configurations, with N₂O-reoxidation being considerable more effective than O₂-reoxidation. It is demonstrated that N₂O reoxidation is capable of completely removing nitridation- induced electron traps, resulting in devices with hot-carrier reliability comparable to N₂O oxide devices. The superior reliability characteristics together with demonstrated improved resistance to boron penetration make N₂O-reoxidized NH₃-nitrided N₂O oxides a very promising gate dielectric candidate for deep- submicrometer dual-gate CMOS applications.

A simple and nondestructive low energy electron beam surface SEM is used in-line to measure the active width with LOCOS isolation. The method resulted in photos with excellent contrast between the silicon and oxide. Also a good correlation between the surface SEM data and electrical measurements is obtained in the submicron region where the active width reduction is a strong function of the LOCOS nitride width. The method can be used to significantly reduce the technology development time by accurately measuring the active width in-line.

in the down-scaling of DRAM (dynamics random access memory) cell size, feature size control becomes a severe problem. Usually we define +/- I 0% of minimum feature size for its process window, e.g., for O.5trn process, its variation should be well controlled within O.O5tm to guarantee production reliability.

A planarized aluminum alloy interconnect has been developed as an alternative to tungsten plugs for a 0.65 (mu) CMOS technology. Contact resistance can increase with either an inadequate RF sputter clean or titanium that is too thin to reduce the native oxide. Diffusion barrier results show that a minimum amount of titanium nitride, whether deposited conventionally or with collimation, is necessary for low junction leakage and good sort yield. Stacked contacts and vias are supported while via resistance and defect density are improved. Electrical bridging due to silicon residues from AlSiCu can be minimized with metal overetching, but not to the extent of AlCu. Sidewall pitting was observed to be due to galvanic corrosion from copper precipitate formation. Overall yield has been improved along with decreased wafer cost compared to conventional tungsten plug technology.

The effect of carrier gases such as nitrogen (N₂) and helium (He) on the properties, growth rate, and conformality of TiN films form tetrakis-diethylamido-titanium (TDEAT) has been investigated. TiN growth rate and properties are significantly influenced by carrier gases. He carrier gas lowers the growth rate and yields the films with low resistivities (approximately equals 2000 (mu) (Omega) -cm) and low level of oxygen contamination. Noted that the resistivity does not increase further upon air-exposure. On the contrary, N₂ carrier gas produces TiN films with relatively high resistivities (<EQ 4000 (mu) (Omega) -cm) and high level oxygen contamination. Moreover, the resistivity continues to change with time. AES analysis shows that the different air-sensitivity of TiN films deposited using two carrier gases is attributed to the presence of oxygen in the films. In addition, TDEAT single sourced process provides the step coverage of 18approximately equals 65% in 2.0 aspect ratio contracts and He carrier gas improves the step coverage slightly, compared with N₂ carrier gas. Furthermore, study of the TDEAT/NH₃ system reveals that sufficient NH₃ addition does not degrade the conformality of TiN films and lowers the resistivity, irrespective of carrier gas.

The formation of multilevel interconnects in GaAs MMIC fabrication depends mainly on the adhesion of the interconnect metals with the intermediate dielectric and with the substrate. The metal lines in our experimental study were formed by depositing multilayer films by rf sputtering technique over spin-coated polyimide and Plasma Enhanced Chemical Vapor Deposited (PECVD) silicon nitride (Si₃N_x). It is observed that samples with a poor adhesion between the second level metal and Si₃N_x show bubbling of blistering in the metal layer when subjected to subsequent high temperature cycles in the fabrication process. It is also found that the choice of certain metal schemes develops a stress between the first level metal and GaAs at the bond pads which peel off at the time of bonding. The present experimental study was undertaken to avoid the loss of the circuit at such advanced stages of fabrication like bonding or second level interconnect formation. The study brings out the dependence of the bondability of the circuit bond pads and the formation of the interconnect lines on the rf sputtering parameters, the premetallization treatment, the choice of the multilayer metal schemes and the thickness of the metals in the multilayer metallization.

As part of our continued studies into improving the performance of multilevel interconnect schemes, we have investigated the film properties and etchability of the AlSiCu/TiN and AlSiCu/TiW film stacks. In this study, two different types of TiN film were deposited by reactive sputtering: low-density (LD) TiN and high-density (HD) TiN. Low-density TiN film was found to have greater oxygen stuffing capability. Both the AlSiCu/TiN and AlSiCu/TiW film stacks can be easily etched anisotropically using high density plasma technology. Barrier integrity of these two film stacks was analyzed by high temperature furnace stress.

As submicron devices continue to shrink, causing increased aspect ratios, gap filling in intermetal dielectric (IMD) becomes more difficult. At the time, global planarization becomes essential to meet the depth of focus budget for photolithography. The paper compares different techniques: Plasma Enhanced-CVD (PECVD) TEOS dep-etch-dep, CVD ozone-TEOS (both subatmospheric and atmospheric), Flowfill^TM (a novel CVD process that uses a silane and hydrogen peroxide chemistry). Gap filling, planarity (local and global) and device performance comparisons are presented. It is concluded that use of the Flowfill^TM, as part of a layer called 'Advanced Planarization Layer' (APL), will save costly planarization steps, while maintaining sort yield and device performance.

This investigation characterized SOG (spin on glass) fully etch back process for submicron multilevel interconnection planarization with the CHF3/CF4 etching chemistry in a conventional RIE (reactive ion etching) oxide etcher. The correlations of SOG fully etch back results with the tool controlled parameters such as pressure, magnetic field strength, bottom electrode temperature, CHF3/CF4 gas flow ratio, and backside helium pressure are completely studied. The selectivity of the PEOX (plasma-enhanced CVD oxide) to SOG and the uniformity of etching are investigated to ensure good planarization performance. It is found that high selectivity of PEOX to SOG process can effectively reduce the microloading effects and improve the planarization during SOG etch back. However, too high selectivity may result in bumped or rough SOG surface. Uniformity is basically affected by the SOG etch rate uniformity, the as-coated SOG thickness variation, and the selectivity. Several approaches are examined to achieve the best uniformity. Finally, with the combination of high selectivity of PEOX to SOG and the uniform etching, good planarization can be achieved in the SOG fully etch back process.

This paper studies the effect of PECVD oxide process in the sandwiched SOG structure for interlevel dielectric applications on MOSFET hot- carrier reliability. Both silane-based oxide (OX) and tetraethylorthosilicate-based oxide (TEOS) were used to form various combinations with SOG as interlevel dielectrics. The influence of N₂O (N₂O-TEOS) and O₂ (O₂-TEOS) as the source gas of oxygen during the PECVD TEOS deposition was also studied. Results indicate that O₂-TEOS/SOG/O₂-TEOS increased the number of electron traps in the gate oxide and deteriorate SiO₂/Si interface characteristics, thus reducing device lifetime. In addition, the use of OX to replace any one of the O₂-TEOS layers improves hot-carrier immunity considerably. Finally, N₂-TEOS/SOG/OX is shown to be a very promising process due to its conformal nature over OX/SOG/OX and improved reliability over O₂-TEOS/SOG/OX.

This work studies the effect of PE-TEOS underlayer on O₃-TEOS based intermetal dielectric (IMD) in terms of gap filling, moisture resistance, and device reliability. PE-TEOS films investigated here were formed by mixed-frequency plasma process and were differed by their reaction oxidizers and/or plasma powers. It is found that the bottom and sidewall step coverages of PE-TEOS vary with processing conditions, with both degrading as nitrogen content or film stress increases. By optimizing the underlayer thickness voidless gap fill has been achieved by O₃-TEOS for 0.5 micrometers generation. To eliminate moisture absorption the deposited O₃-TEOS was then integrated with SOG etchback for planarization. The integrated IMD has been evaluated by hot carrier stressing, which suggests that increasing PE-TEOS stress helps improve device reliability. For a fixed stress, the increased amount of oxygen or nitrogen also help inhibit hot carrier aging. To obtain best device reliability, a tradeoff exists between the moisture resistance and gap filling capability of PE-TEOS underlayer.

Due to the continuing scaling down of minimum feature sizes, interconnect is becoming the limiting factor for on-chip performance. Alternative interconnect designs and new materials are needed to meet future performance expectations as predicted by the SIA Roadmap. We are developing models that can help designers in making initial evaluations about the possible performance impact of advanced interconnect designs and enhanced materials. In this paper, we apply these models to discuss the limitations of interconnect technology. In particular, we focus on the effects of interconnect materials on chip performance issues.

The high demand for advanced, high speed and lower power MPU/ASIC and memory products has boosted the volume and revenue growth of the whole semiconductor industry during the past several years. The evolution of semiconductor technology is also gaining a lot of momentum due to the requirement/competition of the device performance advancement, power supply scaling and the breakthrough of key process equipment and technology. It used to be that memory products drove the new generations of technology. Recently, it is seen that MPU and logic products are driving the performance and density even faster than memories. All products are taking advantage of the technology and equipment advancements to shrink the device for cost reduction and performance enhancement. These new products are being introduced with high speed to the market and to volume production. This fast growing and fast changing environment will provide many challenges to the business management. Some key issues like business environment changes, technology scaling, mass production and management leadership requirements will be discussed in detail.