PROCEEDINGS VOLUME 2636
MICROELECTRONIC MANUFACTURING '95 | 25-27 OCTOBER 1995
Microelectronic Device and Multilevel Interconnection Technology
IN THIS VOLUME

7 Sessions, 33 Papers, 0 Presentations
Section  (10)
MICROELECTRONIC MANUFACTURING '95
25-27 October 1995
Austin, TX, United States
Advanced Device Technologies
Proc. SPIE 2636, Future manufacturing technology in the year 2000, 0000 (15 September 1995); doi: 10.1117/12.221121
Proc. SPIE 2636, Novel LOCOS isolation process for producing highly reliable oxides, 0000 (15 September 1995); doi: 10.1117/12.221131
Proc. SPIE 2636, Latch-up temperature dependence of majority carrier guard structures up to 250-degrees C, 0000 (15 September 1995); doi: 10.1117/12.221140
Proc. SPIE 2636, Plasma charging effects on device degradation from via sputter etch, 0000 (15 September 1995); doi: 10.1117/12.221148
Deep Submicron Devices I
Proc. SPIE 2636, Dimension-temperature combination scaling for low-temperature 0.1micron CMOS, 0000 (15 September 1995); doi: 10.1117/12.221149
Proc. SPIE 2636, 15 ps cryogenic operation of 0.19-um-LG n+ - p+ double-gate SOI CMOS, 0000 (15 September 1995); doi: 10.1117/12.221150
Proc. SPIE 2636, Statistical threshold-voltage variation and its impact on supply-voltage scaling, 0000 (15 September 1995); doi: 10.1117/12.221151
Proc. SPIE 2636, High-frequency BJT-mode operated MOS structure, 0000 (15 September 1995); doi: 10.1117/12.221152
Proc. SPIE 2636, Prediction of 0.18 um CMOS technology performance using tuned device simulation, 0000 (15 September 1995); doi: 10.1117/12.221153
Deep Submicron Devices II
Proc. SPIE 2636, CMOS LDD process with seven masking steps from well to passivation, 0000 (15 September 1995); doi: 10.1117/12.221122
Proc. SPIE 2636, Improved figure-of-merit metric for CMOS transistor performance and its application to 0.25 um CMOS technologies, 0000 (15 September 1995); doi: 10.1117/12.221123
Proc. SPIE 2636, C-V model of the MOS structures with a shallow p-n junction for the electro-physical parameters and profile of the doping determination, 0000 (15 September 1995); doi: 10.1117/12.221124
Memory and Silicide Technologies
Proc. SPIE 2636, Integration of BaxSr1-xTiO3 thin film for DRAM application, 0000 (15 September 1995); doi: 10.1117/12.221125
Proc. SPIE 2636, Optimizing the performance of advanced nonvolatile memories using differentiated cell source and drain implants, 0000 (15 September 1995); doi: 10.1117/12.221126
Proc. SPIE 2636, Optimization of memory redundancy laser link processing, 0000 (15 September 1995); doi: 10.1117/12.221127
Proc. SPIE 2636, Integrity of N2O oxides in WSi2 polycide process, 0000 (15 September 1995); doi: 10.1117/12.221128
Proc. SPIE 2636, Influence of the TiNx/TiSy/poly-Si gate preparation process on MOS-structure properties and reliability, 0000 (15 September 1995); doi: 10.1117/12.221129
Advanced Thin Dielectrics
Proc. SPIE 2636, N2O-based tunnel oxides, 0000 (15 September 1995); doi: 10.1117/12.221130
Proc. SPIE 2636, Improved hot-carrier reliability of MOSFET analog performance with NO-Nitrided SiO2 gate dielectrics, 0000 (15 September 1995); doi: 10.1117/12.221132
Proc. SPIE 2636, Oxide/nitride stacked layers prepared by in situ rapid-thermal multiprocessing, 0000 (15 September 1995); doi: 10.1117/12.221133
Proc. SPIE 2636, Electrical characteristics of n- and p-MOSFETs with N2O-reoxidized NH3-nitrided N2O oxides as gate dielectrics, 0000 (15 September 1995); doi: 10.1117/12.221134
Advanced Device Technologies
Proc. SPIE 2636, In-line LOCOS active width characterization using surface SEM, 0000 (15 September 1995); doi: 10.1117/12.221135
Section
Proc. SPIE 2636, Integral contact process in submicron technology, 0000 (15 September 1995); doi: 10.1117/12.221136
Proc. SPIE 2636, Development and production integration of a planarized AlCu interconnect process for submicron CMOS, 0000 (15 September 1995); doi: 10.1117/12.221137
Proc. SPIE 2636, Formation of TiN films by metal organic chemical vapor deposition using TDEAT, 0000 (15 September 1995); doi: 10.1117/12.221138
Proc. SPIE 2636, Parametral dependence of bilevel-interconnect formation in GaAs ICs/MMICs, 0000 (15 September 1995); doi: 10.1117/12.221139
Proc. SPIE 2636, Submicron patterning of AlSiCu/TiN and AlSiCu/TiW films, 0000 (15 September 1995); doi: 10.1117/12.221141
Proc. SPIE 2636, Comparative study of submicron gap filling and planarization techniques, 0000 (15 September 1995); doi: 10.1117/12.221142
Proc. SPIE 2636, Characterization of SOG (spin on glass) fully etch back process for multilevel interconnection technology, 0000 (15 September 1995); doi: 10.1117/12.221143
Proc. SPIE 2636, Dependence of MOSFET hot-carrier aging on PECVD oxide process, 0000 (15 September 1995); doi: 10.1117/12.221144
Proc. SPIE 2636, Effects of PE-TEOS process on O3-TEOS characteristics and device reliability, 0000 (15 September 1995); doi: 10.1117/12.221145
Proc. SPIE 2636, Modeling limits of multilevel interconnect technology, 0000 (15 September 1995); doi: 10.1117/12.221146
Plenary Session
Proc. SPIE 2636, Manufacturing challenges for sub-half micron technologies, 0000 (15 September 1995); doi: 10.1117/12.221147
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