15 September 1995 Modeling limits of multilevel interconnect technology
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Due to the continuing scaling down of minimum feature sizes, interconnect is becoming the limiting factor for on-chip performance. Alternative interconnect designs and new materials are needed to meet future performance expectations as predicted by the SIA Roadmap. We are developing models that can help designers in making initial evaluations about the possible performance impact of advanced interconnect designs and enhanced materials. In this paper, we apply these models to discuss the limitations of interconnect technology. In particular, we focus on the effects of interconnect materials on chip performance issues.
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Bibiche Geuskens, Bibiche Geuskens, Kenneth Rose, Kenneth Rose, } "Modeling limits of multilevel interconnect technology", Proc. SPIE 2636, Microelectronic Device and Multilevel Interconnection Technology, (15 September 1995); doi: 10.1117/12.221146; https://doi.org/10.1117/12.221146


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