In situ particle monitors (ISPMs) have seen rapidly increased acceptance in semiconductor production because they provide automated, 100% inspection of particle levels during process at a low cost per inspection point. As productivity enhancement tools, ISPM use is only justified when it increases productivity of the host tool. The sensors provide an indirect measure of wafer contamination, and are of greatest value when they provide a particle count that correlates to yield and has identifiable causes. Manufacturing integration has now become the key factor driving the future of ISPM technology. This paper will discuss some of these factors, including correlation, sensor placement, impact on sensor design, application of expertise to qualification and maintenance, and gauge capability.

A critical step in semiconductor wafer fabrication is to halt a plasma reactor as soon as the etched film clears to expose the underlying layer. Typically, changes int he optical emissions spectrum are employed to detect this process endpoint. However, differences in plasma chemistry and reactor chambers, small exposed areas, and variations in wafer patterns complicate this control strategy. Our novel approach uses the characteristic local shape of spectral lines as a guide to finding endpoint. With the Haar wavelet representation, we model shapes over many resolutions. A network of pattern detector 'neutrons' runs real- time to locate these shapes and stop the etch process. This provides robust endpoint detection under widely varying reactor and wafer conditions. Our neural network endpointer has been successfully tested on data gathered for six months at a major wafer fabrication facility.

Semiconductor fabrication lines have become extremely costly, and achieving a good return from such a high capital investment requires efficient utilization of these expensive facilities. It is highly desirable to shorten processing development time, increase fabrication yield, enhance flexibility, improve quality, and minimize downtime. We propose that these ends can be achieved by applying recent advances in the areas of artificial neural networks, fuzzy logic, machine learning, and genetic algorithms. We use the term neural manufacturing to describe such applications. This paper describes our use of artificial neural networks to improve the monitoring and control of semiconductor process.

The Center for Microelectronics Research (CMR) at the University of South Florida has pursued the development of new technologies in the area of high density interconnects. The laser restructuring of electronic circuits, fabricated using standard Very Large Scale Integration (VLSI) process techniques, is an excellent alternative for custom programming of electronic circuits that allows for low cost and quick turn around of the restructured parts. A Laser System for restructuring Electronic Systems has been integrated using state of the art hardware components. This Laser System is fully computer controlled using a newly developed Microsoft Windows based software application running on a 486-66 MHz IBM compatible computer. The laser system consists of a high energy 5 watt Argon CW laser, a 2 watt double frequency pulsed Nd:YAG laser, a blocking shutter, electro-optic shutter (EOS), optic delivery system, a high precision x-y translation stage, and a video camera system used to observe the surface under laser processing. All the system components are mounted on granite table installed on four self leveling pneumatic legs for a vibration free process environment. The z-axis mechanisms consists of a stepper motor based translation stage for automatic focus controls. All control software was written using C++ programming language utilizing the power of readily available plug in boards which provide resources such as: counters, timers, image processing and IEEE-488 interfacing for remote laser control. The control environment exhibits a high degree of consistency with widely accepted visually programmed graphical 'point- and-click' interfaces.

Monitoring process equipment cleanliness with the aid of silicon test wafers and laser scanning detection systems is a highly effective method of process control. These systems detect and locate defects on a substrate with high sensitivity and precision. As integrated circuit manufacturers gain control over environmental contributions to contamination a move toward monitoring the contribution of defects by the process itself is gaining momentum. The additional complexity added to the measurement by the presence of a deposited film, however, requires that users acquire a better understanding of how a laser scanning system generally responds to each of the materials measured. Along with this understanding comes a much wider range of tools available to the user for controlling and understanding the process. With this push to isolate defects contributed by the process has come some interesting applications. Haze, for example, is generally regarded as a measure of the surface roughness. However, in the presence of a dielectric the haze measurement is directly related to the local film reflectivity. This paper discusses the application of two different types of laser scanning systems to the measurement of defects and haze on blanket dielectric films. Included is a brief discussion of the light scattering process in the presence of such films to aid the users of these systems in understanding the measurements they are making. Data from measurements on photoresist and other dielectrics illustrate the effect of the film on the scattering process and a discussion of how to optimize the measurement parameters in this context is included.

Typically metal film processes have been controlled by using monitor wafers. A representative film is deposited on the monitor wafer (witness sample) then the sheet resistance uniformity is measured with a four- point probe. It is assumed that the films on subsequently processed product wafers will have the same characteristics as the film on the monitor. Monitor wafer costs are becoming prohibitive as the industry transitions to 200 millimeter wafers and beyond. Also monitor wafer preparation takes valuable time which could be used for production. Finally monitor wafers also take up valuable space in processing equipment, which could be occupied by product wafers, reducing the overall fab capacity. A mutual inductance technique is described which can be used to measure the sheet resistance of blanket metal films directly on product wafers. This not only reduces the need for sheet resistance monitor wafers and adds system capacity but also gives valuable insight into film properties on the actual product wafer. Data will be presented showing the incorporation of this technique into a 150 millimeter production facility.

In the 25-year history of semiconductor device processing never have we experienced such exciting and challenging times as now relative to the materials aspects of deposition processing technology. With each new milestone in the device processing roadmaps comes new and challenging demands on our ability to deposit electromigration barriers, higher conductivity/lower resistivity metal interconnects, dramatically lower dielectric constant interlevel dielectrics, and higher dielectric constant gate oxides. Our ability to achieve success in these areas is dependent on the cleanliness, performance, and reliability of the materials delivery methods chosen to perform that task.

Process monitoring is now receiving more serious attention than ever before in an effort to increase the efficiency of equipment utilization and the stability of process quality in VLSI production lines. The objectives and effects of process monitoring are discussed in this article. The function of various process monitoring tools are also classified and examined in an effort to replace current PQC or inspection procedures. Several of the monitoring technologies developed by our research group are reviewed in detail. Stabilization of the metal deposition processes is thought to be effective in stabilizing the subsequent etching and photo processes. A sputter monitoring system in which essential process parameters are sensed in-situ is shown to be sensitive enough to detect process variations. W-CVD can be monitored by using quadruple mass spectroscopy (QMS) to provide real-time information about the onset of deposition reactions, etc. Simple time control of the deposition is not sufficient to control the process since the metal CVD reaction is susceptible to the surface state. Process tools can still be improved by the development and application of monitoring technology. However, on overall improvement in production efficiency should be attained through a good combination of process monitoring tools and a line control system.

The photoelectron emission method and the special equipment have been developed to control processes of resistor, silicon dioxide and nitrite thin films. The main idea of the method is based on the difference of work functions of the film and a wafer. It is possible to test structural and phase properties of the films too. The above equipment has been incorporated with the industry instruments providing ion etching.

As semiconductor manufacturing technology advances, there exists a need to review improvements in process monitoring and control. Some of these improvements may be possible by investigating and integrating advanced process sensors. Sensors typically provide information to equipment controllers for proper machine operation. Expanding this definition, a sensor could deliver quality information about the semiconductor product being manufactured. Sensors can provide effective manufacturing line operation, reduced cycle times, and improved product quality. Implementing advanced sensors can also reduce process variability, increase process stability, and provide many other benefits applicable to modern semiconductor production operation. In this paper, a review of the current literature on semiconductor process sensor technology is presented. Much of the literature discusses in-situ measurements for film thickness, particles, and/or other conditions which could affect the quality of the product. Instruments such as RGAs (Residual Gas Analyzers), in-situ film thickness monitors represent current and future advanced sensors. Prior to implementing sensors, it would be ideal to reduce the number of process measurements as much as possible to insure sensor effectiveness. It will be ideal to have working cost of ownership model in place to baseline operations and monitor improvements as sensors move into the production line. There are many new sensors available with highly improved performance, accuracy, and even built-in electronics. These sensors can replace or supplement existing equipment sensors to improve performance, reliability, and extend equipment life. With the increasing costs of maintaining capital equipment, successful implementation could mean substantial savings. These and many other implementation issues are also presented.

During Rapid Thermal Annealing (RTA) of silicon wafers a nonuniform temperature distribution may exist across the wafer caused by a variation of the radiation flux. Due to the thermal gradient, differences in thermal expansion introduce thermal stresses in the material. In a modified RTA system the deformation originating from the thermal stress was monitored by measurement of the wafer curvature using the reflection of a laser beam off the wafer surface. The measurements were performed in real-time by a dedicated image processing system. Silicon wafers were radiatively heated to approximately equals 850 degree(s)C for 90 seconds by halogen lamps at a constant temperature of approximately equals 1740 degree(s)C. The results show that during the complete RTA cycle wafers are in a deformed state. In particular, the deformation is largest during the heating and cooling transients. It is shown that the deformation is reduced by application of radiation shielding.

Chemical vapor deposition, CVD, has assumed an increasing share of the processes utilized in the manufacture of submicron integrated circuits. In addition to the conventional CVD materials such as silicon oxide, nitride and polysilicon, an array of new materials for both dielectric and conductive material applications are in development. For films like BPSG or tungsten, convenient volatile precursor sources exist, however, in other cases temperature sensitive, lower volatility liquids and solids are utilized. The quality and consistency of these molecular precursors can have a marked impact on the film forming process. The application of SPC methodology to precursor manufacture provides an effective metric for controlling both the quality and the consistency of the precursors.

The control of metallization layers' integrity gain more importance increasing the total number of metallization layers. Therefore, an electrical measurement procedure has to separate defectless test structure elements from faulty test structure elements. To decrease the number of test procedures and test equipment, this binary decision will be made parallel to the functional test of product chips using the same digital test system to measure test structure elements too. In addition, the geometrical arrangement of the test structure layout elements will also be transformed to binary description. As a result of this, novel algorithms will now enable the direct comparison of both binary data sets to extract test structure faults like opens and shorts as well as process specific defect parameters.

In an industrial environment, new techniques based on the surface photovoltage measurement (SCA and SPV), are shown to detect sodium, aluminum, iron contamination in the range of E + 10/cm². Variations in the measurements due to wafer samples or oxidation recipe are determined. From these results, a procedure for preparing monitoring samples is established. It is demonstrated that these monitoring tools are useful to monitor equipment but a correlation between the defectivity on a 12 nm gate oxide and SCA and SPV results with the same recipes was not obtained.

The etching gases usually applied for plasma supported gas phase cleaning of PECVD facilities, i.e. CF₄ SF₆ and NF₃, were checked for their efficiency with regard to silicon containing layers. Even less known etching gases such as ClF₃ or pure fluorine were tested. NF₃ has the highest etching rate. The etching rates of F₂ and ClF₃ are only slightly worse. For the first time, etching gas mixtures of CBrF₃/F₂ and NF₃/F₂ were studied. The exhaust gases produced were subjected to online FTIR spectroscopy and evaluated according to their hazards and operator exposure limits. Possible partial recycling of the exhaust gases is discussed.

Ellipsometry has seen only limited application to the post-deposition pattern etch process despite the fact that physical parameters such as groove width, depth and pitch are as critical to product performance as the more basic thin film parameters traditionally analyzed using ellipsometry. This paper presents initial theoretical results pertaining to modeling the reflectance from a 1D etched pattern on a semiconductor substrate. To analyze the sample's effects upon the incident beam polarization, we formulate the zeroth-order reflection coefficients for the orthogonal p and s polarization states and construct models of ellipsometric parameters (Psi and Delta) for a rectangular-groove surface pattern, emphasizing the effect of groove geometry upon these quantities.

The productivity of semiconductor fabs can be improved significantly by the combined action of several measures: Usage of expensive resources only at the point of use, like limiting the generation of a particlefree clean room environment to the immediate surrounding of wafers and wafer processed by usage of mini-environments and SMIF-wafer capsulation. Improvement of the logistic and material flow by an appropriate computer control system in the production line especially for a flexible IC- production. With its new Institute of Silicon Technology (ISiT) in Itzehoe the Fraunhofer-Society for applied research is now realizing an advanced CMOS pilot-line starting with a 0.5 (mu) process that is dedicated from the very beginning for an optimum in flexibility, productivity and lowest running costs. The complete concept for mini- environments, SMIF upgrade of the equipment and production control software was developed in a cooperation between the Fraunhofer institutes for Silicon Technology (ISiT) and Production automation (IPA). The Jenoptic, Jena, was chosen as supplier of SMIF components, mini-environments and identification software. The Line-Information- System, which operates as a low-cost manufacturing execution system, has been developed by the Fraunhofer-IPA using a central database system and client applications to access it. It tracks the actual work in progress in the fab, maintains equipment and lot history and allows production and cost monitoring and optimization.

An investigation was conducted to evaluate various combinations of filter media to minimize boron contamination in clean room environments. Three (mu) PVC fan/blower test chamber modules were constructed, each with a different filter media and placed in a clean room environment. The various media tested included a standard Ultra Low Penetration Air (ULPA), an expanded polytetrafluoroethylene (PTFE) ULPA, and a combination of PTFE with a chemically active prefilter (carbon based). An encapsulation procedure was used to trap airborne contamination on the exposed area of a wafer and sandwich contaminants. The sandwiched contaminants at these controlled interfaces are tested for boron contamination levels. Secondary Ion Mass Spectroscopy (SIMS) was used to determine boron contamination levels at each controlled interface. Results from these experiments were used to quantify the effectiveness of different types of ULPA filters on airborne boron contaminants.

Current trends in semiconductor manufacturing place a large emphasis on monitoring and/or controlling costs. One of the tools used in this effort is cost of ownership modeling. Cost of ownership provides a method to monitor and control costs, evaluation projects, and gain a better understanding into the manufacturing process. From the previous literature on the subject, models can range from very simple to very complex. The need for complexity in this type of model must be evaluated with respect to the actual level of accuracy required. Quality of the data obtained is very important as inaccurate information can lead to potential misuse. From past experience, data collection for modeling can range from being easily accessible to very obscure. In the search for data, various departments such as finance, engineering, facilities, production, and many others must be consulted. the value of the information obtained versus the cost involved in obtaining this information must also be evaluated. In this paper, the development of a cost of ownership model is outlined with the emphasis being placed on the desired goals, the methods used, the sources and manipulation of the data, and a practical example. Future applications of cost of ownership modeling are also discussed as well as integration into a semiconductor production facility.

The field of Information Intellectual System (IIS) application in technology spreads over solving problems, that cannot be easily formalized and that are connected with the diagnostics and quality control of ULSI. One of the main tasks of IIS in the technology of Microelectronics is the precedent search. Another task no less serious is to mathematically process technological experience using information coded array. The purpose of it is, firstly, to establish interrelation between symptomatic and failures and, secondly, to choose an optimal plan of rehabilitation of the technological process and the crystal. The paper describes the basic concepts and principles of software and mathematical software development for computer system of expert diagnostics of technological malfunctions in ULSI manufacturing. The system includes: data base (DB), knowledge base (KB), and subsystems (of precedent search, expert diagnostics and consultations on rehabilitation). DB and KB contain information of defects. The research prototype of this system was realized on IBM PC^3.5.

The transmission electron microscopy (TEM) and high resolution electron microscopy (HREM) are frequently applied for defects and failures ULCI analysis. The preparation of the electron transparent big area flat- parallel semiconductor thin films is needed. The simple and speed automated method of the thin films (less 10 micrometers ) and cross-sections of the multilayer semiconductor structures and devices preparation is described in this paper. It is based on the mechanical and chem- mechanical grinding and polishing of the semiconductor sample with a free abrasive. This method allows to form the flat-parallel and composition uniform thin films with electron transparent area more that 2 mm² after ion-etching treatment. The original equipment which consists of a local treatment unit, planar treatment unit and wire saw unit is developed.

Basic interrelationships among yields, processing environments, and shop-floor scheduling in semiconductor wafer fabrication facilities are currently under study. In this paper, we focus on a hypothetical wafer fabrication facility producing 3D CMOS devices designed and developed at Purdue. A key step of this sequence of this process is silicon selective epitaxial growth (SEG). Our emphasis is on the effects of substrate temperature, and system pressure on the quality of the films grown through silicon SEG. Such studies result in relationships between yield and processing conditions. For example, higher substrate temperatures, in the range of 800 to 1000 degree(s)C studied, appear to result in significantly lower defect densities for all sizes of seed windows investigated. Our experimental observations on relationships between yield and time can in turn can be used to examine the viability of different layouts for wafer fabrication facilities. We focus on cellular layouts, where machines are organized into cells, each dedicated to the processing of a certain subset of operations. For the 3D CMOS fab mentioned previously, we present results of simulation experiments that indicate that under certain conditions, cellular layouts result in better cycle time performance at the expense of some additional capital investment.

The crystallographic orientation of aluminum and titanium planar sputtering targets is shown to influence via bottom coverage and collimation efficiency. A model is developed for predicting the transmission of sputtered atoms through a collimator, based on the measured crystallographic orientation distribution function (ODF). Experimental sputtering results are found to agree with the simulation results. Monte Carlo simulation of step coverage is performed using the angularly resolved sputtering yields derived from the ODF. Improvements in via bottom coverage, greater than 100% (relative), are observed for different crystallographic orientations. The combined effects of crystallographic orientation, target erosion profile, and gas pressure are discussed.

In this paper it is described the techniques and results for contamination control of process chemicals. Two distinct analytical problems are studied: The first concerns the analysis methods of dissolved and insoluble impurities, with the second concerns the analysis of particulate matter separated from the solutions by ultrafiltration techniques to 0.2 microns. The results suggest that considerable quantities of insoluble metallic impurities can be present in semiconductor grade chemicals and that they can be removed by ultrafiltration techniques. In our study we are concerned with the met processing stage including the quality of the chemicals used for developing, reusing, etching, and cleaning procedures in photolithographic processing. In our experience the pure chemical contain considerable quantities of particulate matter. In MOS integrated circuit technologies where the electrical functioning of the devices is surface dependence, the presence of small quantities of specific impurities is even more critical. In order to determinate the quantitive levels of dissolved and particulate impurities present in semiconductor processing chemicals three methods were chosen for their sensitivity and simplicity: (1) Activation analysis, (2) Flamless atomic absorption, and (3) X-ray fluorescence.

The high demand for advanced, high speed and lower power MPU/ASIC and memory products has boosted the volume and revenue growth of the whole semiconductor industry during the past several years. The evolution of semiconductor technology is also gaining a lot of momentum due to the requirement/competition of the device performance advancement, power supply scaling and the breakthrough of key process equipment and technology. It used to be that memory products drove the new generations of technology. Recently, it is seen that MPU and logic products are driving the performance and density even faster than memories. All products are taking advantage of the technology and equipment advancements to shrink the device for cost reduction and performance enhancement. These new products are being introduced with high speed to the market and to volume production. This fast growing and fast changing environment will provide many challenges to the business management. Some key issues like business environment changes, technology scaling, mass production and management leadership requirements will be discussed in detail.