22 March 1996 Model and algorithm for VHDL high-level and hierarchical simulation with debug function
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Proceedings Volume 2644, Fourth International Conference on Computer-Aided Design and Computer Graphics; (1996) https://doi.org/10.1117/12.235495
Event: Fourth International Conference on Computer-Aided Design and Computer Graphics, 1995, Wuhan, China
Abstract
A VHDL simulator with debug function will play a very important role in the area of hardware description and design. The debug function makes the simulation model and the algorithm much more complicated, and sets a still higher demand on the simulator. In this paper an effective hierarchical model and a simulation algorithm suited to debug function requirement are proposed. The hierarchical model and the algorithm support a whole set of VHDL, including behavioral structural and data flow description manner, all kinds of data types of signals and variables, hierarchical component configuration and subprogram call, and to support many kinds of interrupt requirement, on time, condition, component, process, subprogram and statement line.
© (1996) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jinain Bian, Jinain Bian, Feng Lu, Feng Lu, Bo Wan, Bo Wan, Ming Su, Ming Su, } "Model and algorithm for VHDL high-level and hierarchical simulation with debug function", Proc. SPIE 2644, Fourth International Conference on Computer-Aided Design and Computer Graphics, (22 March 1996); doi: 10.1117/12.235495; https://doi.org/10.1117/12.235495
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