Novel architectures for implementing very high throughput variable-length decoders in HDTV systems

Michael Bakhmutsky

doi:10.1117/12.235413

22 March 1996 Novel architectures for implementing very high throughput variable-length decoders in HDTV systems

Michael Bakhmutsky

Proceedings Volume 2668, Digital Video Compression: Algorithms and Technologies 1996; (1996) https://doi.org/10.1117/12.235413
Event: Electronic Imaging: Science and Technology, 1996, San Jose, CA, United States

Abstract

Variable Length Decoders (VLD) constitute one of the principal bottlenecks in building HDTV Decoders. In these systems, the VLD must decode at a rate of about 100 million code words per second or higher. The VLD speed of operation, however, is limited by long propagation delays in the word length decoding loop caused by wide barrel shifting, large table decoding, multiplexing, and arithmetic operations. The stringent speed requirements present major challenges in VLD implementation using current VLSI technology. Several techniques of VLD throughput enhancement are discussed here. Some of these methods increase the speed of the loop hardware, while the others introduce some parallelism in processing the inherently serial bit stream data. These techniques can be combined together or used independently to provide advantages in different applications. The techniques of Type-Independent Length Decoding Loop Acceleration and Scaleable Quasi-Parallel Processing produce very good results in professional applications (studio, medical etc.). For consumer applications, the One-Hot architecture along with the technique of Adaptive Acceleration in Processing of Huffman Coded Bit Streams promise to deliver feasible and inexpensive VLD implementations in VLSI with the benefit of operation at clock rates lower than those required in the architectures traditionally employed. A method of Dynamic State Machine Partitioning in Tree Searching VLD implementations is also considered for a `pre-VLD' application, where word boundary information is extracted to enhance the performance of the actual VLD.

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Michael Bakhmutsky "Novel architectures for implementing very high throughput variable-length decoders in HDTV systems", Proc. SPIE 2668, Digital Video Compression: Algorithms and Technologies 1996, (22 March 1996); https://doi.org/10.1117/12.235413

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KEYWORDS

Clocks

Parallel processing

Multiplexers

Surgery

Very large scale integration

Multiplexing

Control systems

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