The architecture of a terabit free-space photonic backplane for parallel computing and communications is described. The photonic backplane interconnects typically 32 printed circuit boards or multichip modules (PCBs or MCMs) and has a bisection bandwidth in the terabit/sec range, with each PCB/MCM receiving a fraction of the peak bandwidth. The backplane consists of a large number of parallel reconfigurable optical channels spaced a few hundred microns apart. The parallel channels can be organized as a multi-channel ring where the channel access protocols are implemented by smart pixel arrays. Smart pixel arrays are integrated opto-electronic devices with optical I/O and with electronic processing capabilities. A smart pixel array which supports multiple reconfigurable broadcast channels and which transports terabits of optical data per second (Tb/s) and filters and extracts hundreds of gigabits of electrical data per second (Gb/s) for each PCB or MCM is proposed. Projections for free-space optical backplane capacities over the next decade are outlined. Within a decade, free-space optical technologies have the potential to support aggregate capacities of the order of 10s of Tb/s. It is also shown that optical technologies have the potential to result in significant reductions in volume and increases in performance when compared to conventional electrical architectures.
Ted H. Szymanski,
"Photonic backplane architecture for broadband switching", Proc. SPIE 2692, Optical Interconnects in Broadband Switching Architectures, (20 March 1996); doi: 10.1117/12.235862; https://doi.org/10.1117/12.235862