27 May 1996 Mix-and-match lithography processes for 0.1-um MOS transistor device fabrication
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Abstract
The mix-and-match method is an effective method to meet the requirements of minimizing the exposure time and the feature size, in which only the critical gate layer is exposed by electron beam lithography system, and the other ones by conventional g-line stepper. The negative type chemically amplified resist SAL601, made by Shipley, has been used for gate fabrication. The optimum conditions for the electron beam lithography including mark dimension, resist process and etching process have been investigated. The accelerating voltage and the beam current were fixed to be 40 kV and 0.25 nA, respectively. The mark of the electron beam lithography has the trench cross shape of 0.5 micrometers in depth, 20 micrometers in length and 3 micrometers in width. The sensitivity of SAL601 resist has been 20 (mu) C/cm2 for 0.1 micrometers patterning at 40 kV accelerating voltage. The polysilicon gate was etched by electron cyclotron resonance with SiO2 thin mask in HBr/O2 gas, for the appropriate anisotropy of etching and for the polysilicon-to-oxide selectivity of HBr/O2 gas plasma. The well defined profile of polysilicon gate with 0.1 micrometers width has been obtained successfully.
© (1996) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jen Yu Yew, Jen Yu Yew, Lih Juann Chen, Lih Juann Chen, Kazumitsu Nakamura, Kazumitsu Nakamura, Tien Sheng Chao, Tien Sheng Chao, Horng-Chih Lin, Horng-Chih Lin, } "Mix-and-match lithography processes for 0.1-um MOS transistor device fabrication", Proc. SPIE 2723, Electron-Beam, X-Ray, EUV, and Ion-Beam Submicrometer Lithographies for Manufacturing VI, (27 May 1996); doi: 10.1117/12.240468; https://doi.org/10.1117/12.240468
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