Optimization of i-line resist process for 0.5-um polysilicon gate structures using a top-coat layer

Jean-Paul E. Chollet; Marie-Therese Basso

doi:10.1117/12.241873

14 June 1996 Optimization of i-line resist process for 0.5-μm polysilicon gate structures using a top-coat layer

Jean-Paul E. Chollet; Marie-Therese Basso

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Proceedings Volume 2724, Advances in Resist Technology and Processing XIII; (1996) https://doi.org/10.1117/12.241873
Event: SPIE's 1996 International Symposium on Microlithography, 1996, Santa Clara, CA, United States

Abstract

For the manufacturing of 0.5 micrometer devices and below, the control of the gate CD must be accurate to guarantee the yield of circuits. To overcome the swing curve effect, a dyed resist gives a partial answer. The profiles and the resolution of the resist are decreased. The reduction of swing curve is not adequate. A top antireflective coating (TARC) is a recent industrial solution. The process is not complex, the throughput is maintained and there is not a modification of the hardware of the track. The thickness of the resist coated over the topography (LOCOS 250 nm) is however not equal. Consequently, the thickness of the TARC AQUATAR must be adjusted to 64 nm over topography to the minimum swing ratio (R₁ reduced to zero). This paper studies the influence of the thickness of AQUATAR and the thickness of the resist on the final CD after etching over topography. To minimize the CD range of gate structure due to swing curve effect it is found necessary to modify the thickness of top arc from 64 nm to 45 nm over topography.

Citation Download Citation

Jean-Paul E. Chollet, Jean-Paul E. Chollet, Marie-Therese Basso, Marie-Therese Basso, } "Optimization of i-line resist process for 0.5-μm polysilicon gate structures using a top-coat layer", Proc. SPIE 2724, Advances in Resist Technology and Processing XIII, (14 June 1996); doi: 10.1117/12.241873; https://doi.org/10.1117/12.241873

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