21 May 1996 Wafer flatness modeling for scanning steppers
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Model-based analysis is used to explain previous observations regarding the distributional form and numeric relationships of several key lithographic flatness quality metrics for silicon wafers. The dominant relationships are controlled by longer wavelength (tens of millimeters) surface topography, while the distribution shapes are controlled by shorter wavelength (few millimeters) topography. A lithographic flatness modeling framework is introduced which can provide guidance for specification of silicon wafer flatness for ULSI IC products. New site flatness models show that, compared to a full-field stepper, a scanning stepper can effect improved flatness performance from wafers of similar quality.
© (1996) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Randal K. Goodall, Howard R. Huff, "Wafer flatness modeling for scanning steppers", Proc. SPIE 2725, Metrology, Inspection, and Process Control for Microlithography X, (21 May 1996); doi: 10.1117/12.240143; https://doi.org/10.1117/12.240143

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