27 February 1996 Architectures for high-speed re-synchronization using parallel pattern matching
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Proceedings Volume 2727, Visual Communications and Image Processing '96; (1996) https://doi.org/10.1117/12.233312
Event: Visual Communications and Image Processing '96, 1996, Orlando, FL, United States
Abstract
A variable length coder adds a synchronization code having a fixed length to a bit stream for fast resynchronization after transmission error or random access. In this paper, we present architectures for high speed resynchronization with a desired bit pattern such as synchronization code from an input bit stream. We consider the hardware architecture for achieving parallel pattern matching and apply it to VLD of the video decoder. The hardware architectures are constructed to minimize the time taken for one stage in the system for finding match pattern. It can rapidly deal with the transmission error and random access through high speed resynchronization.
© (1996) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Sanghoon Lee, Sanghoon Lee, Soon Hwa Jang, Soon Hwa Jang, Soon Hong Kwon, Soon Hong Kwon, } "Architectures for high-speed re-synchronization using parallel pattern matching", Proc. SPIE 2727, Visual Communications and Image Processing '96, (27 February 1996); doi: 10.1117/12.233312; https://doi.org/10.1117/12.233312
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