27 February 1996 Improvement of VLSI architecture for two-dimensional discrete cosine transform and its inverse
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Proceedings Volume 2727, Visual Communications and Image Processing '96; (1996) https://doi.org/10.1117/12.233318
Event: Visual Communications and Image Processing '96, 1996, Orlando, FL, United States
Abstract
This paper presents an improvement of VLSI architecture for 2-dimensional DCT (discrete cosine transform) and its inverse in complexity and speed. In the proposed architecture, an accuracy compensator and a bit serial transposition network are newly introduced. It can be easily applied to the previously developed 2-D DCT/IDCT architectures, and revised to more fast and simple architecture without changing the existing scheme. Its other main characteristic is that this scheme jumps over the restriction of the computational resolution for the finite word length calculation. Bit serial transposition network needs less registers and more simple routing than the existing architectures. The proposed architecture shows operation speed over 100 MHz in 0.6 micrometer 3-metal CMOS technology.
© (1996) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kyeounsoo Kim, Kyeounsoo Kim, Soon Hwa Jang, Soon Hwa Jang, Soon Hong Kwon, Soon Hong Kwon, Kyung Sik Son, Kyung Sik Son, } "Improvement of VLSI architecture for two-dimensional discrete cosine transform and its inverse", Proc. SPIE 2727, Visual Communications and Image Processing '96, (27 February 1996); doi: 10.1117/12.233318; https://doi.org/10.1117/12.233318
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