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27 June 1996 PtSi FPA with improved CSD operation
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Abstract
Over the past ten years we have been developing PtSi focal plane arrays (FPAs) using the charge sweep device (CSD). FPAs are going to high resolution and the power of the FPAs are on an upward trend. Now we have developed a low-power CMOS CSD scanner (LOCCS) for a high resolution FPA. The conventional CSD scanner operates at the same frequency as that of the horizontal CCD to prevent fixed pattern noise (FPN), and generates a frequency pulse higher than the minimum requirement. The LOCCS is a kind of CMOS dynamic shift resistor, which generates clock pulses for vertical signal transfer without the low frequency input pulses that cause FPN. Because the LOCCS generates multi-phase clock pulses, the power consumption can be reduced. We have fabricated test devices to evaluate the improved CSD operation by the LOCCS, and confirmed that the devices operate normally and the reduction of power consumption is in good agreement with the theory. We also applied the LOCCS to a 256 by 256 PtSi FPA and obtained thermal images.
© (1996) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Tadashi Shiraishi, Hirofumi Yagi, Kazuyo Endo, Masafumi Kimata, Tatsuo Ozeki, Keisuke Kama, and Toshiki Seto "PtSi FPA with improved CSD operation", Proc. SPIE 2744, Infrared Technology and Applications XXII, (27 June 1996); https://doi.org/10.1117/12.243489
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