7 June 1996 TMS320C8x family architecture and future roadmap
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The TMS320C8x family of Digital Signal Processors (DSP) incorporate multiple, high performance, fully programmable, processors onto a single CMOS die. The 320C80 has four 16/32-bit integer DSP CPUs, a 32-bit Floating Points RISC processor, 50 K bytes of SRAM, and a crossbar bus that can support over 4 Gigabytes of bandwidth. The 320C82 includes two of the integer DSPs, the RISC processor, 44 K bytes of SRAM, and a crossbar bus that can sustain over 2.6 Gigabytes of bandwidth per second. The C8x devices have special features that support general signal processing, telecommunication processing, and image processing. In addition to integrating multiple processors, the architecture includes on-chip Data RAM and instruction caches, as well as a very intelligent DMA controller, that support very high performance applications using lower cost off-chip memory. This paper concludes with a brief discussion of some of the future directions for this family of processors.
© (1996) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Karl Guttag, "TMS320C8x family architecture and future roadmap", Proc. SPIE 2750, Digital Signal Processing Technology, (7 June 1996); doi: 10.1117/12.241977; https://doi.org/10.1117/12.241977


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