14 June 1996 VLSI modified architecture for reduced symmetric fuzzy Singleton set and its applications
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A general-purpose fuzzy logic inference engine for real time control applications has been designed, the core of which is based on a modified reduced symmetric fuzzy singleton set (MRSFSS) structure combining the advantages of small fuzzy memory for a maximum storing capacity of 730 rule-base. The MRSFSS structure can provide up to three input variables, a maximum of nine membership functions for each input variable, and produces two output values. The innovation of FLC chip is the definition feature of the MRSFSS structure which alleviates the drawbacks of existing fuzzy inference engine and enables the entire FLC chip to be performed on a 1.2 micrometer CMOS VLSI single chip. Although the hardware of FLC engine is simplified, the structure itself can incorporate a wide class of applications since many systematic and heuristic approaches can be cast into the MRSFSS structure with an even more simplified approach and most equal performances. Moreover, a guide tour is provided through the aspects of generating the fuzzy IF-THEN rules, based on a proposed architecture for controlling a wide class of objects whose dynamics are approximated by first- order and second-order transfer functions.
© (1996) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Saleh M. Abdel-hafeez, Saleh M. Abdel-hafeez, Scott A. Starks, Scott A. Starks, } "VLSI modified architecture for reduced symmetric fuzzy Singleton set and its applications", Proc. SPIE 2761, Applications of Fuzzy Logic Technology III, (14 June 1996); doi: 10.1117/12.243254; https://doi.org/10.1117/12.243254


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